Apparatus and method for improving input/output throughput of memory system

ABSTRACT

This technology relates to a method and apparatus for improving I/O throughput through an interleaving operation for multiple memory dies of a memory system. A memory system may include: multiple memory dies suitable for outputting data of different sizes in response to a read request; and a controller in communication with the multiple memory dies through multiple channels, and suitable for: performing a correlation operation on the read request so that the multiple memory dies interleave and output target data corresponding to the read request through the multiple channels, determining a pending credit using a result of the correlation operation, and reading, from the multiple memory dies, the target data corresponding to the read request and additional data stored in a same storage unit as the target data, based on a type of the target data corresponding to the read request and the pending credit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.16/856,111 filed on Apr. 23, 2020, which claims benefits of priority ofKorean Patent Application No. 10-2019-0108164 filed on Sep. 2, 2019. Thedisclosure of each of the foregoing application is incorporated hereinby reference in its entirety.

BACKGROUND 1. Field

Various embodiments of the invention relate to a memory system, and moreparticularly, to a method and an apparatus for improving datainput/output performance through an interleaving operation on memorydies in the memory system.

2. Discussion of the Related Art

Recently, a computer environment paradigm has shifted to ubiquitouscomputing, which enables a computer system to be accessed anytime andeverywhere. As a result, the use of portable electronic devices such asmobile phones, digital cameras, notebook computers and the likeincreases. Such portable electronic devices typically use or include amemory system that uses or embeds at least one memory device, i.e., adata storage device. The data storage device can be used as a mainstorage device or an auxiliary storage device of a portable electronicdevice.

In a computing device, unlike a hard disk, a data storage deviceembodied as a nonvolatile semiconductor memory device is advantageous inthat it has excellent stability and durability because it has nomechanical driving part (e.g., a mechanical arm), and has high dataaccess speed and low power consumption. Examples of such a data storagedevice include a universal serial bus (USB) memory device, a memory cardhaving various interfaces, and a solid state drive (SSD).

SUMMARY

An embodiment of the disclosure may provide a memory system, a dataprocessing system, and an operation process or a method, which mayquickly and reliably process data into a memory device by reducingoperational complexity and performance degradation of the memory system,thereby enhancing efficiency of the memory device.

In addition, an embodiment of the disclosure may provide a method and anapparatus for inputting and outputting plural pieces of data to and froma plurality of memory dies in a memory system in an interleaving formatto improve data input/output performance (e.g., I/O throughput) of thememory system.

Further, an embodiment of the disclosure may provide a memory systemwhich limitation not limited to a physical location in which a piece ofdata is to be stored for an interleaving operation, in a process ofstoring the piece of data in a plurality of memory dies, therebyeffectively utilizing the plurality of memory dies in the memory systemso that an operation stability and a lifespan of a memory system may beimproved.

In addition, an embodiment of the disclosure may provide an apparatusand a method for dynamically determining whether to proceed or stop acorrelation operation to plural requests based on a configuration of amemory system and/or characteristics of the correlation operation, whichinfluences an operation such as reading or writing data performed in thememory system, so that overhead in operations performed in the memorysystem may be reduced.

Also, various embodiments are directed to the provision of a method andapparatus, which can improve operation efficiency of a memory system bydetermining the availability of additional data capable of being outputalong with target data based on the type of target data for which readhas been requested and reading the target data and the additional datatogether from a memory die through one read operation based on a pendingcredit associated with the execution or stop of a correlation operationif the availability is a given reference or more.

In addition, an embodiment of the disclosure may provide a memory systemincluding an address allocation scheme which reduces resources used forthe correlation operation and supports an interleaving operation to aplurality of memory dies in the memory system, thereby increasing anoperational efficiency of the memory system.

In accordance with an embodiment of the present invention, a memorysystem may include: multiple memory dies suitable for outputting data ofdifferent sizes in response to a read request; and a controller incommunication with the multiple memory dies through multiple channels,and suitable for: performing a correlation operation on the read requestso that the multiple memory dies interleave and output target datacorresponding to the read request through the multiple channels,determining a pending credit using a result of the correlationoperation, and reading, from the multiple memory dies, the target datacorresponding to the read request and additional data stored in a samestorage unit as the target data, based on a type of the target datacorresponding to the read request and the pending credit.

Each of the multiple memory dies may include multiple blocks eachcomprising multiple pages each comprising multiple sections eachcomprising multiple memory cells and a page buffer suitable for cachingdata read from the multiple blocks, in page units, and each of themultiple memory dies may output data in section units or page units fromthe page buffer in response to the read request.

The controller may determine the pending credit based on whether aprevious correlation operation has been performed prior to selectiontiming, whether the previous correlation operation was successful, andoperating states of the multiple memory dies at the selection timing,the selection timing may indicate the time at which candidate readrequests are selected as a target of the correlation operation among aplurality of base read requests.

If the candidate read request is a read request of a section unit, whenprocessing the candidate read request, the controller may read, from themultiple memory dies, the target data corresponding to the candidateread request and the additional data stored in the same storage unitbased on a type of the target data corresponding to the candidate readrequest and the pending credit at a processing timing, which is a timeat which the candidate read request is processed, and the storage unitmay be a page.

When the candidate read request is a read request of a section unit andthe target data corresponding to the candidate read request issequential data that is read-requested through an internal operation,the controller: may read the target data corresponding to the candidateread request and the additional data together from the same page whenthe pending credit at the processing timing is a first reference valueor more, and may read only the target data corresponding to thecandidate read request when the pending credit at the processing timingis less than the first reference value.

When the candidate read request is a read request of a section unit andthe target data corresponding to the candidate read request is randomdata that is read-requested through an internal operation or data thatis read-requested by a host, the controller may read only the targetdata corresponding to the candidate read request.

The controller may be further suitable for determining whether toperform the correlation operation on the candidate read request selectedat the selection timing, based on a type of target data corresponding tothe candidate read request selected at the selection timing and thepending credit at the selection timing.

When the target data of the candidate read request selected at theselection timing is data that is read-requested through an internaloperation or random data that is read-requested by a host, thecontroller may perform the correlation operation on the candidate readrequest selected at the selection timing when the pending credit at theselection timing is the second reference value or more.

The controller: may decrease the pending credit when at least one of themultiple memory dies is in an idle state at the selection timing, mayincrease the pending credit when a previous candidate read request isprocessed without the correlation operation prior to the selectiontiming, may increase the pending credit when the previous correlationoperation succeeded and decreases the pending credit when the previouscorrelation operation failed, and may reset the pending credit to aninitial value when the candidate read request is not selected for areference time or more after the determining of whether to perform thecorrelation operation.

In accordance with an embodiment of the present invention, an operatingmethod of a memory system comprising multiple memory dies capable ofoutputting data of different sizes in response to a read request, theoperating method may include: performing a correlation operation on theread request so that the multiple memory dies interleave and outputtarget data corresponding to the read request through multiple channels,determining a pending credit using a result of the correlationoperation; and reading, from the multiple memory dies, target datacorresponding to the read request and additional data stored in a samestorage unit as the target data, based on a type of the target datacorresponding to the read request and the pending credit.

Each of the multiple memory dies may include multiple blocks eachcomprising multiple pages each comprising multiple sections eachcomprising multiple memory cells and a page buffer suitable for cachingdata read from the memory cells in page units, and each of the multiplememory dies may output the read data in section units or page units fromthe page buffer in response to the read request.

In the determining, the pending credit may be determined based onwhether a previous correlation operation has been performed prior toselection timing, whether the previous correlation operation wassuccessful, and operating states of the multiple memory dies at theselection timing, the selection timing may indicate the time at whichcandidate read requests are selected as a target of the correlationoperation among a plurality of base read requests.

In the reading, when the candidate read request is a read request of asection unit, when the candidate read request is processed, the targetdata corresponding to the candidate read request and the additional datastored in the same storage unit may be read together from the multiplememory dies based on a type of the target data corresponding to thecandidate read request and the pending credit at a processing timing,which is a time at which the candidate read request is processed, andthe storage unit may be a page.

The reading may include: reading the target data corresponding to thecandidate read request and the additional data together from the samepage when the pending credit at the processing timing is a firstreference value or more when the candidate read request is a readrequest of a section unit and the target data corresponding to thecandidate read request is sequential data that is read-requested throughan internal operation; reading only the target data corresponding to thecandidate read request when the pending credit at the processing timingis less than the first reference value when the candidate read requestis a read request of a section unit and the target data corresponding tothe candidate read request is sequential data that is read-requestedthrough an internal operation; and reading only the target datacorresponding to the candidate read request when the candidate readrequest is a read request of a section unit and the target datacorresponding to the candidate read request is random data that isread-requested through an internal operation or data that isread-requested by a host.

The operating method may further include determining whether to performthe correlation operation on the candidate read request selected at theselection timing, based on a type of data corresponding to the candidateread request selected at the selection timing and the pending credit atthe selection timing.

The performing of the correlation may include: performing thecorrelation operation on the candidate read request selected at theselection timing when the target data of the candidate read requestselected at the selection timing is data that is read-requested throughan internal operation or random data that is read-requested by a hostand when the pending credit at the selection timing is the secondreference value or more.

The determining may include: decreasing the pending credit when at leastone of the multiple memory dies is in an idle state at the selectiontiming; increasing the pending credit when a previous candidate readrequest is processed without the correlation operation prior to theselection timing; increasing the pending credit when the previouscorrelation operation succeeded; decreasing the pending credit when theprevious correlation operation failed; and resetting the pending creditto an initial value when the candidate read request is not selected fora reference time or more after the determining of whether to perform thecorrelation operation.

The operating method may further include: identifying, in a firsttransmission operation, a target address for a read request correlateddue to a success of the correlation operation and transmitting thetarget address to the multiple memory dies through the multiplechannels; receiving, in a first receiving operation, data correspondingto the correlated read request in an interleaving manner through themultiple channels after the first transmission operation; identifying,in a second transmission operation, a target address for a read requestnot correlated due to a failure of the correlation operation andtransmitting the target address to the multiple memory dies; receiving,in a second receiving operation, from the multiple memory dies, datacorresponding to the not-correlated read request after the secondtransmission operation; and outputting, to an external apparatus, thedata received in the first or second receiving operation.

In accordance with an embodiment of the present invention, a memorysystem may include: a memory device including plural dies, each havingplural pages, each having plural sections; and a controller electricallycoupled to the dies through plural channels respectively and suitablefor providing the dies with read commands requesting data to be readfrom sections of different offsets within the respective dies, andcontrolling the dies to read the requested data according to a full syncinterleaving scheme, the controller may control each of the dies toperform a read operation in units of the sections or in units of thepages according to a type of a corresponding read command among theprovided read commands.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are block diagrams illustrating a memory system inaccordance with an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a data processing systemincluding a memory system in accordance with an embodiment of thepresent invention.

FIG. 3 is a block diagram illustrating a controller in a memory systemin accordance with another embodiment of the present invention.

FIG. 4 is a block diagram illustrating an internal structure of a memorydevice.

FIG. 5A and FIG. 5B illustrate characteristics of a correlationoperation performed by a controller.

FIG. 6 is a block diagram illustrating an internal structure of thecontroller.

FIGS. 7 to 9 are flowcharts describing an example of a method foroperating a memory system.

FIG. 10 illustrates an operation of the controller depending on the typeof data.

FIGS. 11A to 11C illustrate an operation of the controller for multipleread requests.

DETAILED DESCRIPTION

Various examples of the disclosure are described below in more detailwith reference to the accompanying drawings. Aspects and features of thepresent invention, however, may be embodied in different ways to formother embodiments, including variations of any of the disclosedembodiments. Thus, the invention is not to be construed as being limitedto the embodiments set forth herein. Rather, the described embodimentsare provided so that this disclosure is thorough and complete and fullyconveys the disclosure to those skilled in the art to which thisinvention pertains. Throughout the disclosure, like reference numeralsrefer to like parts throughout the various figures and examples of thedisclosure. It is noted that reference to “an embodiment,” “anotherembodiment” or the like does not necessarily mean only one embodiment,and different references to any such phrase are not necessarily to thesame embodiment(s).

It will be understood that, although the terms “first”, “second”,“third”, and so on may be used herein to identify various elements,these elements are not limited by these terms. These terms are used todistinguish one element from another element that otherwise have thesame or similar names. Thus, a first element in one instance could betermed a second or third element in another instance without indicatingany change in the element itself.

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When an element is referred to as beingconnected or coupled to another element, it should be understood thatthe former can be directly connected or coupled to the latter, orelectrically connected or coupled to the latter via one or moreintervening elements therebetween. In addition, it will also beunderstood that when an element is referred to as being “between” twoelements, it may be the only element between the two elements, or one ormore intervening elements may also be present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit the invention. As usedherein, singular forms are intended to include the plural forms and viceversa, unless the context clearly indicates otherwise. Similarly, theindefinite articles “a” and “an” mean one or more, unless it is clearfrom the language or context that only one is intended.

It will be further understood that the terms “comprises,” “comprising,”“includes,” and “including” when used in this specification, specify thepresence of the stated elements and do not preclude the presence oraddition of one or more other elements. As used herein, the term“and/or” includes any and all combinations of one or more of the listeditems.

Unless otherwise defined, all terms including technical and scientificterms used herein have the same meaning as commonly understood by one ofordinary skill in the art to which the invention belongs in view of thedisclosure. It will be further understood that terms, such as thosedefined in commonly used dictionaries, should be interpreted as having ameaning that is consistent with their meaning in the context of thedisclosure and the relevant art, and not be interpreted in an idealizedor overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the invention. Theinvention may be practiced without some or all of these specificdetails. In other instances, well-known process structures and/orprocesses have not been described in detail in order not tounnecessarily obscure the invention.

It is also noted, that in some instances, as would be apparent to thoseskilled in the relevant art, a feature or element described inconnection with one embodiment may be used singly or in combination withother features or elements of another embodiment, unless otherwisespecifically indicated.

Embodiments of the disclosure are described in detail below withreference to the accompanying drawings, wherein like numbers referencelike elements.

FIGS. 1A and 1B are block diagrams illustrating a memory system inaccordance with an embodiment of the present invention. In a computingdevice or a mobile device embedded with the memory system 110, a host(e.g., host 102 of FIG. 2) may be engaged with the memory system 110 fordata input/output (I/O) operations. The host is an external deviceoperatively engaged with the memory system 110.

Referring to FIG. 1A, the memory system 110 may include a controller 130and a memory device 150. The controller 130 may output data, which isrequested by the host 102 and delivered from the memory device 150, orstore data inputted from the host 102 in the memory device 150.Furthermore, the controller 130 may internally generate data in order tomanage an operation of storing or outputting the data of the host 102,and may store or output the data in or to the memory apparatus 150. Thememory device 150 may include a plurality of non-volatile memory cells,each capable of storing data. Here, an internal structure and/orconfiguration of the memory device 150 may vary depending on theapplicable specification or desired performance of the memory device150, which, in turn, may be based on the purpose(s) for which the memorysystem 110 is used or the requirement(s) of the host 102.

The controller 130 and the memory device 150 may be coupled through aplurality of data paths. The memory device 150 may include a pluralityof memory dies 240A, 240B, 240C, 240D, which may be coupled with thecontroller 130 through different data paths. The first memory die 240Aand the controller 130 are coupled through a first channel (CH1) and afirst way (W1) CH1W1, and the second memory die 240B and the controller130 are coupled through the first channel (CH1) and a second way (W2)CH1W2. The first memory die 240A and the second memory die 240B mayshare the first channel CH1, but the first memory die 240A and thesecond memory die 240B may use different ways W1, W2 independently. Inaddition, the third memory die 240C and the controller 130 are coupledthrough the second channel (CH2) and the first way (W1) CH2W1, and thefourth memory die 240D and the controller 130 are coupled via the secondchannel (CH2) and the second way (W2) CH2W2. The number of channelsand/or ways constituting the data paths between the controller 130 andthe memory device 150 may vary depending on the number of memory dies inthe memory device 150. The number of channels and ways connecting thememory dies 240A, 240B, 240C, 240D to the controller 130 may bedifferent, according to the purpose(s) of the memory system 110 orrequirement(s) of the host 102.

Referring to FIG. 1B, each of the multiple memory dies 240A, 240B, 240C,and 240D may include multiple pages PAGE0, PAGE1, PAGE2, . . . eachincluding multiple memory cells, multiple blocks BLOCK000, BLOCK001,BLOCK002, . . . , BLOCK010, BLOCK011, BLOCK012, . . . each includingmultiple pages PAGE0, PAGE1, PAGE2 . . . , and a plurality of planesPLANE00 and PLANE01 each including a subset of all of the blocks of thememory device 150. Furthermore, each of the multiple memory dies 240A,240B, 240C, and 240D may include page buffers PB000, PB001, PB002, . . ., PB010, PB011, PB012, . . . for caching data input to or output fromthe blocks BLOCK000, BLOCK001, BLOCK002, . . . , BLOCK010, BLOCK011,BLOCK012, . . . , respectively, in units of pages.

Furthermore, each of the pages PAGE0, PAGE1, PAGE2, . . . may include aset number of sections SECTION0, SECTION1, SECTION2, and SECTION3. Thatis, the sum of all memory cells included in each of the sectionsSECTION0, SECTION1, SECTION2, and SECTION3 may be with the same as thenumber of memory cells included in one of the pages PAGE0, PAGE1, PAGE2,. . . . Furthermore, each of the page buffers PB000, PB001, PB002, . . ., PB010, PB011, PB012, . . . may include a set number of section pagebuffers PB_SEC0, PB_SEC1, PB_SEC2, and PB_SEC3, in accordance with eachof the pages PAGE0, PAGE1, PAGE2, . . . each including the set number ofsections SECTION0, SECTION1, SECTION2, and SECTION3. an amount of dataless than a page can be input or output through the aforementionedconfiguration in which each of the pages PAGE0, PAGE1, PAGE2, . . .includes the sections SECTION0, SECTION1, SECTION2, and SECTION3. Forexample, assuming that four sections SECTION0, SECTION1, SECTION2, andSECTION3 are included in one page as in FIG. 1B, in order to input oroutput data in units of pages, the data may be input or output using allof the four sections SECTION0, SECTION1, SECTION2, and SECTION3 and thecorresponding four section page buffers PB_SEC0, PB_SEC1, PB_SEC2, andPB_SEC3. In order to input or output data in a unit smaller than a pageunit, that is, in unit(s) of a section, the data may be input or outputselecting only three or two or one of the four sections SECTION0,SECTION1, SECTION2, and SECTION3. In this case, data not selected fordata input or output may have been stored in the remaining section(s),that is excluding section(s) that has/have been selected for data inputor output.

If data is output from some sections of the sections, it is possible touse a method of reading all data stored in those sections, caching theread data in the corresponding section page buffers, selecting andoutputting only data cached in section page buffers that belong to thesection page buffers that correspond to the selected sections, anddeleting data, cached in the remaining section page buffers that havenot been selected, without outputting the data. As described above, ifan operation of inputting or outputting data in a unit smaller than apage unit, that is, in a section unit, is supported in addition to anoperation of inputting or outputting data in a page unit, the time takenfor a read operation may be different depending on from how manysections data is read through one read operation.

For example, if data is read from the first and second sections SECTION0and SECTION1 of the four sections, after all of the data of the foursections is cached in the four section page buffers PB_SEC0, PB_SEC1,PB_SEC2, and PB_SEC3, only the data of the first and second section pagebuffers PB_SEC0 and PB_SEC1 will be output. If data is read from all ofthe four sections SECTION0, SECTION1, SECTION2, and SECTION3, after allof the data of the four sections is cached in the four section pagebuffers PB_SEC0, PB_SEC1, PB_SEC2, and PB_SEC3, the data of all of thefour section page buffers will be output. In this case, there may be atime difference between the operation of outputting only the data of thetwo section page buffers PB_SEC0 and PB_SEC1 of the four section pagebuffers and the operation of outputting the data of all of the foursection page buffers PB_SEC0, PB_SEC1, PB_SEC2, and PB_SEC3. Regardlessof whether data is read from the two sections SECTION0 and SECTION1 ordata is read from all of the four sections, the data of all of the foursections needs to be cached in the four section page buffers PB_SEC0,PB_SEC1, PB_SEC2, and PB_SEC3. Accordingly, the time necessary to readdata from the four sections SECTION0, SECTION1, SECTION2, and SECTION3may be less than two times the time necessary to read data from the twosections SECTION0 and SECTION1. For example, the time necessary to readdata from the four sections SECTION0, SECTION1, SECTION2, and SECTION3may be about 1.4 times the time necessary to read data from the twosections SECTION0 and SECTION1.

For reference, FIG. 1B illustrates a detailed configuration of the firstmemory die 240A of the multiple memory dies 240A, 240B, 240C, and 240D.The remaining memory dies 240B, 240C, and 240D (not illustrated) mayhave the same configuration as the first memory die 240A.

Referring to FIG. 1A, the plurality of memory dies 240A, 240B, 240C,240D in the memory device 150 may be configured as different modules andindependently coupled with the controller 130 via different data paths.When multiple data paths are used for data exchange, the plurality ofmemory dies 240A, 240B, 240C, 240D and the controller 130 may use aninterleaving scheme via the multiple data paths for exchanging data toincrease speed of data transfer.

For the interleaving scheme to enhance the speed of data transferbetween the memory device 150 and the controller 130, data to be storedis distributed over several modules rather than in a single module. Inexecuting an interleaving scheme, a memory system may use an addresslimitation structure or an address scheme for distributing and storingplural pieces of new data over and in a plurality of modules of thememory device 150. For example, when programming four pieces of data,the conventional memory system stores the four pieces of data in fourmemory dies individually. Here, the number of pieces of data may referto the number of data units which may be stored together by a singleprogram operation or a single write operation can be performed. Forexample, when a program operation (or a write operation) in a unit ofpage is performed, four pieces of data may include an amount of dataprogrammed in four pages.

In order to increase operational efficiency of program and readoperations and enhance distributed storage, a memory system may employan address limitation structure. In the address limitation structure,when four pieces of data are programmed in four memory dies, the samephysical location in each memory die is allocated. For example, whenstoring the four pieces of data in the four memory dies, each of thefour pieces of data may be individually stored in a fifth physicallocation of a respective one of the four memory dies. Thereafter, wheneight pieces of data are programmed, the eight pieces of data may bestored in the sixth and seventh physical locations of each memory die.Here, the physical location may indicate a block or a page in a memorydie.

When storing five pieces of data in four memory dies in a memory systemwith the address limitation structure, two pieces of data may be storedin first and second physical locations of one memory die, and threepieces of data may be individually stored in a first physical locationof the other three memory dies respectively. In the memory system withthe address limitation structure, three pieces of dummy data areindividually written in a second physical location of the remainingthree memory dies because a piece of data inputted along with the nextprogram request cannot be subsequently written in the second physicallocation of the other three memory dies.

When a memory system has an address limitation structure for aninterleaving operation, operational efficiency may be degraded becausepieces of dummy data may be programmed whenever a program operation withodd pieces of data, or a number of pieces of data that does not matchthe number of memory dies, is performed. In addition, because eachmemory die does not always have the same operation state (in terms ofhealth, wear, etc.), the memory system may independently perform anadditional operation to compensate for each memory die condition, whichmay increase overhead. In other words, an operation condition thataffects one memory die may delay memory operations for associated memorydies involved in the same interleaving operation.

The memory system 110 according to an embodiment of the disclosureadopts a full sync interleaving structure which is capable of supportinginterleaving operations between the controller 130 and the memory device150 without an address limitation structure. The full sync interleavingstructure does not have an address limitation for storing data at thesame location in each of a plurality of memory dies 240A, 240B, 240C,240D in the memory device 150. The controller 130 may distribute piecesof data to be programmed according to an operation condition and anoperation state of each memory die. In doing so, the pieces of data neednot be evenly distributed among the memory dies. For example, if one ofthe four memory dies 240A, 240B, 240C, 240D (say memory die 240A) cannotprogram a piece of data immediately due to an internal operation beingperformed within, the controller 130 may transfer data to the remainingmemory dies (e.g., 240B, 240C, 240D). The controller 130 may distributedata over the plurality of memory dies 240A, 240B, 240C, 240D toincrease efficiency of data transmission and reduce an operation marginof a program operation without applying a strict rule such as theaddress limitation structure. In addition, in a memory system 110according to an embodiment, it is unnecessary to program dummy data, asis the case in a memory system with the address limitation structure.

After the controller 130 transfers a piece of data into the memorydevice 150 and the piece of data is programmed in the memory device 150,the controller 130 may generate or update map information associating alogical address with a physical location (physical address)corresponding to the data. In addition, the controller 130 may storegenerated or updated map information in the memory device 150.

Because the memory system 110 does not adopt the address limitationstructure as described above, it might be hard to guarantee that datatransmission between the controller 130 and the memory device 150 in aprocess of reading and outputting plural pieces of data requested by anexternal device, e.g., a host, performed in an interleaving format(interleaved). Accordingly, the controller 130 may include correlationcircuitry 194 for correlating a plurality of read operations requestedby the host so that plural pieces of data outputted from the memorydevice 150 by the plurality of read operations may be interleaved.

Referring to FIG. 1A, the controller 130 may include an input/output(I/O) buffer control circuitry 198, a correlation circuitry 194, anoperation control circuitry 196, a pending credit determining circuitry195, a monitoring circuitry 197, and a read mode selection circuitry199.

As used in this disclosure, the term ‘circuitry’ may refer to one ormore of (a) hardware-only circuit implementations, such asimplementations in only analog and/or digital circuitry (b) combinationsof circuits and software (and/or firmware), such as: (i) a combinationof processor(s) or (ii) portions of processor(s)/software includingdigital signal processor(s), software, and memory that work together tocause an apparatus, such as a mobile phone or server, to perform variousfunctions and (c) to circuits, such as a microprocessor or a portion ofa microprocessor, that uses software or firmware, even if the softwareor firmware is not physically present. As a further example, the term“circuitry” may refer to one or more processor or portion of a processorand accompanying software and/or firmware. The term “circuitry” mayrefer to an integrated circuit for a storage device.

The I/O buffer control circuitry 198 may control an input buffer inwhich a command or data from the host or a command or data generatedwithin the controller has been temporarily stored and/or an outputbuffer in which data corresponding to a command from the host or acommand generated within the controller has been temporarily stored. Forexample, when the host transmits a read request (or read command) forfifteen pieces of data to the memory system 110, the controller 130 maystore the read request in the input buffer, may receive, from the memoryapparatus 150, the fifteen pieces of data corresponding to the readrequest, may temporarily store the fifteen pieces of data in the outputbuffer, and then may output the fifteen pieces of data to the host.Furthermore, the controller 130 may internally generate a read requestfor five pieces of data, may store the read request in the input buffer,may receive, from the memory apparatus 150, the five pieces of datacorresponding to the read request, may temporarily store the five piecesof data in the output buffer, and then may use the five pieces of datafor an operation within the controller 130. The I/O buffer controlcircuitry 198 may recognize how many read requests have been stored inthe input buffer. The I/O buffer control circuitry 198 may recognize howmany data has been stored in the output buffer.

The operation control circuitry 196 may identify a physical location ofthe memory apparatus 150 where read-requested data is stored, and mayread the read-requested data from the identified physical location. If aread request stored in the input buffer has been received from the host,a logical address corresponding to the read request may have included inthe read request. In such a case, the operation control circuitry 196may translate the logical address into a physical address based on mapinformation in accordance with the read request (or read command) andthe logical address received from the input buffer, and may request thedata of the physical address from the memory apparatus 150. If a readrequest stored in the input buffer has been internally generated andtransmitted by the controller, a physical address corresponding to theread request may have been included in the read request. In such a case,the operation control circuitry 196 may identify the physical addressreceived from the input buffer, and may request, from the memoryapparatus 150, data corresponding to the read request. In this case, thephysical address may indicate a specific location within the multiplememory dies 240A, 240B, 240C, and 240D of the memory apparatus 150. Ifthe operation control circuitry 196 performs a read request in orderstored in the input buffer, a physical address may randomly indicate oneof the multiple memory dies 240A, 240B, 240C, and 240D. In this case, aninterleaving operation may or may not be performed.

When the I/O buffer control circuitry 198 determines that data to beoutput to the host is stored in the output buffer, it may transmit, tothe correlation circuitry 194, a read request (or read command) storedin the input buffer. The correlation circuitry 194 may check mapinformation regarding the plural logical addresses corresponding to theplural read requests from the I/O buffer control circuitry 198 tocorrelate the plural read requests, so that the operation controlcircuitry 196 may perform plural read operations corresponding to theplural read requests according to an interleaving scheme, e.g., pluralpieces of data are interleaved between the plurality of memory dies240A, 240B, 240C, 240D. Herein, a correlation operation performed by thecorrelation circuitry 194 may support parallel processing anddistributed computing between the controller 130 and the plurality ofmemory dies 240A, 240B, 240C, 240D. When a single data path is shared byplural components, the plural components may interleave their signals ortheir data in the single data path. Further, when plural data paths areused by a single component, the single component may distribute pluralsignals or plural data over the plural data paths. The correlationoperation may enable some of a plurality of read requests to bedelivered into the plurality of memory dies in parallel through theplurality of channels, so that plural pieces of data corresponding tothe plurality of read requests are outputted in parallel from theplurality of memory dies via the plurality of channels. The correlationoperation for a plurality of read requests may include that pluralpieces of data requested to the memory dies 240A, 240B, 240C, 240D maybe transferred from the memory device 150 to the controller 130according to an interleaved format.

For example, it is assumed that the host requests fifteen pieces of datastored in the memory apparatus 150 and requests five pieces of datagenerated within the controller 130. The controller 130 may receive aread request for the fifteen pieces of data from the host, and maygenerate a read request for the internally generated five pieces ofdata. Furthermore, the I/O buffer control circuitry 198 may transmit the20 read requests for the twenty pieces of data to the correlationcircuitry 194. The correlation circuitry 194 performs correlationoperation on the 20 read requests for the twenty pieces of data. Thecorrelation circuitry 194 tries to correlate the 20 read requests sothat at least some of the twenty pieces of data are outputted accordingto an interleaving scheme. For example, the correlation circuitry 194may check a physical address corresponding to a first logical addressinputted along with a first read request among the 20 read requests, andrecognize that first data corresponding to the first logical address isstored in the first memory die 240A. The correlation circuitry 194 maycheck a physical address corresponding to a second logical addressinputted along with a second read request among the 20 read requests.When second data corresponding to the second read request is stored inthe third memory die 240C or the fourth memory die 240D, an interleavingoperation between the first and second read requests may be expectedbecause the first data and the second data respectively corresponding tothe first and second read requests may be transmitted via differentchannels CH1, CH2. Thus, the first and second read requests may becorrelated by the correlation circuitry 194, and correlated readrequests may be transmitted to the operation control circuitry 196.

However, if the second data is stored in the first memory die 240A orthe second memory die 240B, the interleaving operation between the firstand second read requests may not be expected because the first data andthe second data respectively corresponding to the first and second readrequests may be transmitted via the same channel CH1. In this case, thecorrelation circuitry 194 may not pair or correlate the first and secondread requests. Then, the correlation circuitry 194 may check a physicaladdress for a third read request. When third data corresponding to thethird read request is stored in the third memory die 240C or the fourthmemory die 240D, an interleaving operation between the first request andthe third request may be expected because the first data and the thirddata respectively corresponding to the first and third read requests maybe transmitted via different channels CH1, CH2. The correlationcircuitry 194 may correlate the first read request and the third readrequest and transmit the correlated read request to the operationcontrol circuitry 196. The third read request may be transmitted earlierthan the second read request.

However, if the third data is stored in the first memory die 240A or thesecond memory die 240B, the interleaving operation between the firstrequest and the third request may not be expected because the first andthird data are transmitted via the same channel. In this case, thecorrelation circuitry 194 may check a physical address for a fourth readrequest.

As described above, the correlation circuitry 194 may check a physicallocation where data corresponding to a read request is stored, correlatesome of read requests when an interleaving operation between the readrequests may be expected, and transfer correlated read requests to theoperation control circuitry 196. For the correlation operation, thecorrelation circuitry 194 may refer to map information in the controller130 or loaded in a memory or a buffer of the controller 130.

The correlation operation with respect to a plurality of read requests,which is performed by the correlation circuitry 194, may adverselyaffect data input/output performance such as I/O throughput of thememory system 110 because the correlation operation may cause a delay.

Accordingly, the I/O buffer control circuitry 198 may not transmit, tothe correlation circuitry 194, all of read requests received from thehost or generated within the controller 130. That is, the I/O buffercontrol circuitry 198 may select at least some second read requests(candidate read requests) among a plurality of base read requestsreceived from the host 102 or generated within the controller, and maytransmit only the candidate read requests to the correlation circuitry194. For example, although the memory system 110 identifies data to beoutput from the output buffer to the host and the correlation circuitry194 performs a correlation operation, the I/O buffer control circuitry198 may transmit, to the correlation circuitry 194, a read requestreceived from the host or generated within the controller only when itis determined that the transmission of the read request does notinfluence data I/O throughput of the memory system 110. Each of the baseand candidate read requests may be any normal read request directing thememory apparatus 150 to read target data therefrom. The I/O buffercontrol circuitry 198 may receive the base read request from the host102. The base read request may be selected as the candidate read requestby the I/O buffer control circuitry 198. The base and candidate readrequests are described in more detail with reference to FIGS. 11A to11C.

Furthermore, the correlation circuitry 194 may not perform correlationoperation on any of the candidate read requests received from the I/Obuffer control circuitry 198. That is, the correlation circuitry 194 mayor may not perform a correlation operation on a candidate read requestreceived from the I/O buffer control circuitry 198 based on a pendingcredit. For example, when a pending credit is a reference value or more,the correlation circuitry 194 may perform a correlation operation on acandidate read request received from the I/O buffer control circuitry198. In contrast, when the pending credit is less than the referencevalue, the correlation circuitry 194 may not perform a correlationoperation on the candidate read request received from the I/O buffercontrol circuitry 198. In this case, the pending credit may be used asan index by which a probability, possibility, pattern or trend for thecorrelation operation of the candidate read request can be predictedwhen the correlation circuitry 194 performs the correlation operation onthe candidate read request received from the I/O buffer controlcircuitry 198. Based on such a pending credit, the controller 130 canimprove efficiency of an internal operation by avoiding the execution ofan unnecessary correlation operation or a correlation operation thatcauses overhead within the memory system 110.

Furthermore, a correlation operation performed by the correlationcircuitry 194 may succeed or fail depending on a physical location ofdata corresponding to a candidate read request received from the I/Obuffer control circuitry 198. If an interleaving operation for thephysical location of the data corresponding to the candidate readrequest is predicted, it may be said that a correlation operationperformed by the correlation circuitry 194 has been successful. Thecandidate read request correlated by the correlation circuitry 194 maybe transmitted to the operation control circuitry 196 in the correlatedstate due to the success of the correlation operation. However, if aninterleaving operation for the physical location of data correspondingto the candidate read request is not predicted, it may be said that acorrelation operation performed by the correlation circuitry 194 hasfailed. The candidate read request not correlated by the correlationcircuitry 194 may be transmitted to the operation control circuitry 196in the uncorrelated state due to the failure of the correlationoperation. Furthermore, it may not be necessary to determine whether toperform a correlation operation performed by the correlation circuitry194 based on the type of data corresponding to a candidate read requestreceived from the I/O buffer control circuitry 198. That is, if datacorresponding to a candidate read request received from the I/O buffercontrol circuitry 198 is sequential read-requested data, the correlationcircuitry 194 may not perform a correlation operation on the candidateread request. The reason for this is that if read data requested by thehost 102 is sequential data, the amount of such data is highly likely tobe relatively large and the data is highly likely to be distributed andstored in multiple memory dies in an interleaving manner even when thedata is written in the memory apparatus 150. Accordingly, although thecorrelation circuitry 194 does not perform a separate correlationoperation, a plurality of sequentially input candidate read requests arehighly likely to be read in an interleaving manner. For example,multiple read requests corresponding to files having a relatively highcapacity, such as a movie or music, may correspond to sequential readdata requested by the host 102.

When a candidate read request is selected from the base read requests,the pending credit determining circuitry 195 may determine a pendingcredit based on whether a previous correlation operation has beenperformed prior to selection timing at which the candidate read requestis selected, whether the previous correlation operation is successfulprior to the selection timing, and operating states of the multiplememory dies 240A, 240B, 240C, and 240D at the selection timing. In thiscase, the operating states of the multiple memory dies 240A, 240B, 240C,and 240D may be recognized by the monitoring circuitry 197. That is,when a candidate read request to be transmitted from the I/O buffercontrol circuitry 198 to the correlation circuitry 194 is selected, thepending credit determining circuitry 195 may adjust a value of a pendingcredit based on whether a previous correlation operation has beenperformed by the correlation circuitry 194 prior to selection timing atwhich the candidate read request is selected, whether an executedcorrelation operation has been successful if the correlation operationhas been performed, and an operating states of the multiple memory dies240A, 240B, 240C, and 240D at the selection timing.

The state in which a value of the pending credit is sufficiently higherthan a reference value may mean that an operation margin of thecontroller 130 is sufficient. That is, this may mean that although thecorrelation circuitry 194 performs a correlation operation, it may nothave a bad influence on data I/O throughput of the memory system 110.

When a value of a pending credit is sufficiently higher than a referencevalue as described above, the controller 130 may read, from the multiplememory dies 240A, 240B, 240C, and 240D, target data corresponding to aread request and additional data stored in the same storage unit as thetarget data, separately from a correlation operation performed by thecorrelation circuitry 194. The same storage unit may be a page. Thetarget data and the additional data may be stored in sections within thesame page. That is, when a value of the pending credit is sufficientlyhigher than the reference value, the controller 130 may perform acorrelation operation on at least some of multiple read requestsreceived from the host or generated within the controller, and may read,from the multiple memory dies 240A, 240B, 240C, and 240D, target datacorresponding to the at least some of the multiple read requests andadditional data stored in the same storage unit as the target data. Inthis case, although the pending credit is sufficiently higher than thereference value, the controller 130 may read the additional data alongwith the target data only when the type of target data corresponding toa read request is a predefined type. In this case, a reference value ofthe pending credit, that is, a criterion for whether to perform acorrelation operation on the read request, and a reference value, thatis, a criterion for whether to read the additional data along with thetarget data corresponding to the read request, may be different. Forexample, assuming that a reference value, that is, a criterion forwhether to read additional data along with target data corresponding toa read request, is a first reference value and a reference value of apending credit, that is, a criterion for whether to perform acorrelation operation on the read request, is a second reference value,the first reference value and the second reference value may be equal ordifferent. Furthermore, the first reference value may be greater orsmaller than the second reference value.

In other words, when a pending credit is sufficiently higher than areference value, the controller 130 may read, from the multiple memorydies 240A, 240B, 240C, and 240D, additional data stored in the samestorage unit as the target data depending on the type of target datacorresponding to a read request.

In this case, all of a plurality of base read requests received from thehost or generated within the controller may be read requests for thetarget data. However, the state in which a pending credit issufficiently higher than a reference value may be assumed as the statein which at least some candidate read requests of the plurality of baseread requests are selected and a correlation operation is frequentlyperformed on the selected candidate read requests. A separate additionaloperation that is performed on read requests not selected as a target ofthe correlation operation in the state in which the correlationoperation is frequently performed as described above may be aninefficient operation. Accordingly, the controller 130 may perform anoperation of selecting whether to read target data and additional datatogether or read only the target data on only the candidate read requestthat belongs to the plurality of base read requests and that has beenselected as a target of a correlation operation. In such a case, a firstreference value of a pending credit, that is, a criterion for whether toread additional data along with target data corresponding to a readrequest, may be identical with or higher than a second reference valueof the pending credit, that is, a criterion for whether to perform acorrelation operation on the read request. For reference, the controller130 may also perform an operation of selecting whether to read targetdata and additional data together or whether to read only the targetdata on a read request that belongs to the plurality of base readrequests and that has not been selected as a target of a correlationoperation.

Referring to the relation between the pages and the sections illustratedin FIG. 1B, target data corresponding to a read request and additionaldata stored in the same storage unit as the target data may be defined.Specifically, if the target data corresponding to the read request isdata from a particular section, the data of all pages in that section inaddition to the requested section in which the target data has beenstored may be cached in a page buffer. An operation of selecting andoutputting only data of some sections, among data of a page unit alreadycached in the page buffer, in a section unit and an operation ofoutputting all data of the page unit may be similar in their operationcontrol methods, and may not have a great difference in their processingtime. Accordingly, when data corresponding to a read request is definedas target data, additional data stored in the same storage unit as thetarget data may be data stored in the same page as the target data.

This is described again with reference to FIG. 1B. If a candidate readrequest that belongs to a plurality of base read requests and that hasbeen selected as a correlation operation target is a read request of asection unit that is smaller than a page unit, when the controller 130processes the candidate read request, the controller 130 may read, fromthe multiple memory dies 240A, 240B, 240C, and 240D, target datacorresponding to the candidate read request and additional data storedin the same page as the target data together based on the type of targetdata corresponding to the candidate read request and a pending credit atthe processing timing of the candidate read request.

If a read request transmitted from the correlation circuitry 194 to theoperation control circuitry 196 is a read request of a section unit, theread mode selection circuitry 199 may select a read mode based on thetype of target data corresponding to the transmitted read request and apending credit at the transmission timing of the read request. The readmode selected by the read mode selection circuitry 199 as describedabove may be applied to the operation control circuitry 196, and may beapplied when the read request received from the correlation circuitry194 is processed.

That is, the operation control circuitry 196 may identify a physicallocation of the memory apparatus 150 where read-requested data isstored, and may read the read-requested data from the identifiedphysical location by applying the read mode selected by the read modeselection circuitry 199.

The controller 130 may perform a correlation operation on at least someof multiple read requests received from the host or generated within thecontroller in accordance with an operating environment so that thetransmission of data between the memory apparatus 150 and the controller130 is performed through interleaving. In addition, the memory system110 does not have to adopt an address limitation structure forexchanging signals or data according to an interleaving scheme withinthe memory system 110. Plural pieces of data may be distributed andstored based on operation environment and operation states of theplurality of memory dies 240A, 240B, 240C, 240D in the memory device150. The controller 130 may attempt to correlate read requests forreading plural pieces of data stored in the plurality of memory dies240A, 240B, 240C, 240D in the memory device 150. Because the memorysystem 110 does not have to use the address limitation structure, theplurality of memory dies 240A, 240B, 240C, 240D in the memory device 150may be operated more efficiently, and lifespans of the plurality ofmemory dies 240A, 240B, 240C, 240D in the memory device 150 may beimproved. On the other hand, since data may be interleaved in memorydies 240A, 240B, 240C, 240D, the memory system 110 according to anembodiment of the disclosure can avoid deteriorating the datainput/output performance (e.g., I/O throughput) thereof.

FIG. 2 is a block diagram illustrating a data processing systemincluding a memory system in accordance with an embodiment of thepresent invention.

Referring to FIG. 2, the data processing system 100 may include a host102 engaged or operably coupled with a memory system 110.

The host 102 may include any of a variety of portable electronicdevices, such as a mobile phone, an MP3 player and a laptop computer, oran electronic device such as a desktop computer, a game player, atelevision (TV), a projector and the like.

The host 102 also includes at least one operating system (OS), which cangenerally manage, and control, functions and operations performed in thehost 102. The OS may provide interoperability between the host 102engaged with the memory system 110 and the user of the memory system110. The OS may support functions and operations corresponding to user'srequests. By way of example but not limitation, the OS may include ageneral operating system and a mobile operating system according tomobility of the host 102. The general operating system may be split intoa personal operating system and an enterprise operating system accordingto system requirements or user's environment. The personal operatingsystem, including Windows and Chrome, may be subject to support servicesfor general purposes. The enterprise operating systems may bespecialized for securing and supporting high performance, includingWindows servers, Linux and Unix. Further, the mobile operating systemmay include an Android and iOS. The mobile operating system may besubject to support services or functions for mobility (e.g., a powersaving function). The host 102 may include a plurality of operatingsystems. The host 102 may execute multiple operating systems incooperation with the memory system 110, corresponding to a user'srequest. The host 102 may transmit a plurality of commands correspondingto the user's requests into the memory system 110, thereby performingoperations corresponding to commands within the memory system 110.Handling plural commands in the memory system 110 is described belowwith reference to FIGS. 4 and 5.

The memory system 110 may perform a specific function or operation inresponse to a request from the host 102 and, particularly, may storedata to be accessed by the host 102. The memory system 110 may be usedas a main memory system or an auxiliary memory system of the host 102.The memory system 110 may be implemented with any one of various typesof storage devices, which may be electrically coupled with the host 102,according to a protocol of a host interface. Non-limiting examples ofsuitable storage devices include a solid state drive (SSD), a multimediacard (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), amicro-MMC, a secure digital (SD) card, a mini-SD, a micro-SD, auniversal serial bus (USB) storage device, a universal flash storage(UFS) device, a compact flash (CF) card, a smart media (SM) card and amemory stick.

The storage devices for the memory system 110 may be implemented with avolatile memory device, for example, a dynamic random access memory(DRAM) or a static RAM (SRAM), and/or a nonvolatile memory device suchas a read only memory (ROM), a mask ROM (MROM), a programmable ROM(PROM), an erasable programmable ROM (EPROM), an electrically erasableprogrammable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-changeRAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (RRAM orReRAM) or a flash memory.

The memory system 110 may include a controller 130 and a memory device150. The memory device 150 may store data to be accessed by the host102. The controller 130 may control storage of data in the memory device150.

The controller 130 and the memory device 150 may be integrated into asingle semiconductor device, which may be included in any of the varioustypes of memory systems as described above.

By way of example but not limitation, the controller 130 and the memorydevice 150 may be integrated into a single semiconductor device. Thecontroller 130 and memory device 150 may be integrated to form an SSDwith improved operation speed. When the memory system 110 is used as anSSD, the operating speed of a host 102 connected to the memory system110 can be improved more than that of a host 102 connected with a harddisk. In another embodiment, the controller 130 and the memory device150 may be integrated into one semiconductor device to form a memorycard, such as a PC card (PCMCIA), a compact flash card (CF), a smartmedia card (e.g., SM, SMC), a memory stick, a multimedia card (e.g.,MMC, RS-MMC, MMCmicro), a secure digital (SD) card (e.g., SD, miniSD,microSD, SDHC), or a universal flash memory.

The memory system 110 may be configured as a part of, for example, acomputer, an ultra-mobile PC (UMPC), a workstation, a net-book, apersonal digital assistant (PDA), a portable computer, a web tablet, atablet computer, a wireless phone, a mobile phone, a smart phone, ane-book, a portable multimedia player (PMP), a portable game player, anavigation system, a black box, a digital camera, a digital multimediabroadcasting (DMB) player, a 3-dimensional (3D) television, a smarttelevision, a digital audio recorder, a digital audio player, a digitalpicture recorder, a digital picture player, a digital video recorder, adigital video player, a storage configuring a data center, a devicecapable of transmitting and receiving information under a wirelessenvironment, one of various electronic devices configuring a homenetwork, one of various electronic devices configuring a computernetwork, one of various electronic devices configuring a telematicsnetwork, a radio frequency identification (RFID) device, or one ofvarious components configuring a computing system.

The memory device 150 may be a nonvolatile memory device and may retaindata stored therein even while electrical power is not supplied. Thememory device 150 may store data provided from the host 102 through awrite operation, while providing data stored therein to the host 102through a read operation. The memory device 150 may include a pluralityof memory blocks 152, 154, 156, each of which may include a plurality ofpages. Each of the plurality of pages may include a plurality of memorycells to which a plurality of word lines (WL) are electrically coupled.The memory device 150 also includes a plurality of memory dies, each ofwhich includes a plurality of planes, each of which includes memoryblocks, among the plurality of memory blocks 152, 154, 156. In addition,the memory device 150 may be a non-volatile memory device, for example aflash memory, and the flash memory may have a three-dimensional stackstructure.

The controller 130 may control overall operations of the memory device150, such as read, write, program and erase operations. For example, thecontroller 130 may control the memory device 150 in response to arequest from the host 102. The controller 130 may provide data, readfrom the memory device 150 to the host 102. The controller 130 may storedata provided by the host 102 into the memory device 150.

The controller 130 may include a host interface (I/F) 132, a processor134, error correction code (ECC) circuitry 138, a power management unit(PMU) 140, a memory interface (I/F) 142 and a memory 144, alloperatively coupled via an internal bus.

The host interface 132 may process commands and data provided from thehost 102, and may communicate with the host 102 through at least one ofvarious interface protocols, such as universal serial bus (USB),multimedia card (MMC), peripheral component interconnect-express (PCI-eor PCIe), small computer system interface (SCSI), serial-attached SCSI(SAS), serial advanced technology attachment (SATA), parallel advancedtechnology attachment (PATA), small computer system interface (SCSI),enhanced small disk interface (ESDI) and integrated drive electronics(IDE). In accordance with an embodiment, the host interface 132 is acomponent for exchanging data with the host 102, which may beimplemented through firmware called a host interface layer (HIL).According to an embodiment of the present invention, the host interface132 may include the I/O buffer control circuitry 198 described abovewith reference to FIG. 1A.

The ECC circuitry 138 may correct error bits of the data to be processedin (e.g., outputted from) the memory device 150. To that end, the ECCcircuitry 138 may include an ECC encoder and an ECC decoder. Here, theECC encoder may perform error correction encoding of data to beprogrammed in the memory device 150 to generate encoded data into whicha parity bit is added and store the encoded data in memory device 150.The ECC decoder may detect and correct errors contained in data readfrom the memory device 150 when the controller 130 reads the data storedin the memory device 150. In other words, after performing errorcorrection decoding on the data read from the memory device 150, the ECCcircuitry 138 may determine whether the error correction decoding hassucceeded and output an instruction signal (e.g., a correction successsignal or a correction fail signal). The ECC circuitry 138 may use theparity bit which is generated during the ECC encoding process, forcorrecting the error bit of the read data. When the number of error bitsis greater than or equal to a threshold number of correctable errorbits, the ECC circuitry 138 may not correct error bits but instead mayoutput an error correction fail signal indicating that the error bitsare uncorrectable.

The ECC circuitry 138 may perform an error correction operation based ona coded modulation such as a low density parity check (LDPC) code, aBose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS)code, a convolution code, a recursive systematic code (RSC), atrellis-coded modulation (TCM), or a Block coded modulation (BCM). TheECC circuitry 138 may include any and all circuits, modules, systems ordevices for performing the error correction operation based on at leastone of the above described codes.

The PMU 140 may manage electrical power in the controller 130. Forexample, the PMU 140 may detect power-on and power-off. In addition, thePMU 140 may include a power detector.

The memory interface 142 may serve as an interface for handling commandsand data transferred between the controller 130 and the memory device150, to allow the controller 130 to control the memory device 150 inresponse to a request delivered from the host 102. The memory interface142 may generate a control signal for the memory device 150 and mayprocess data entered into or outputted from the memory device 150 underthe control of the processor 134 in a case when the memory device 150 isa flash memory and, in particular, when the memory device 150 is a NANDflash memory. The memory interface 142 may provide an interface forhandling commands and data between the controller 130 and the memorydevice 150, for example, operations of NAND flash interface, inparticular, operations between the controller 130 and the memory device150. In accordance with an embodiment, the memory interface 142 may beimplemented through firmware called a flash interface layer (FIL) as acomponent for exchanging data with the memory device 150.

The memory 144 may support operations performed by the memory system 110and the controller 130. The memory 144 may store temporary ortransactional data generated or delivered for operations in the memorysystem 110 and the controller 130. The controller 130 may control thememory device 150 in response to a request from the host 102. Thecontroller 130 may deliver data read from the memory device 150 into thehost 102. The controller 130 may store data entered through the host 102within the memory device 150. The memory 144 may be used to store dataused by the controller 130 and the memory device 150 to performoperations such as read operations or program/write operations.

The memory 144 may be a volatile memory. The memory 144 may beimplemented with a static random access memory (SRAM), a dynamic randomaccess memory (DRAM) or both. Although FIG. 2 shows memory 144 disposedwithin the controller 130, embodiments are not limited to thatarrangement. That is, the memory 144 may be within or external to thecontroller 130. For instance, the memory 144 may be an external volatilememory having a memory interface transferring data and/or signalsbetween the memory 144 and the controller 130.

The memory 144 may store data for performing operations such as datawriting and data reading requested by the host 102 and/or data transferbetween the memory device 150 and the controller 130 for backgroundoperations such as garbage collection and wear levelling. In accordancewith an embodiment, for supporting operations in the memory system 110,the memory 144 may include a program memory, a data memory, a writebuffer/cache, a read buffer/cache, a data buffer/cache and a mapbuffer/cache.

The processor 134 may be a microprocessor or a central processing unit(CPU). The memory system 110 may include one or more processors 134. Theprocessor 134 may control the overall operations of the memory system110. By way of example but not limitation, the processor 134 can controla program operation or a read operation of the memory device 150, inresponse to a write request or a read request entered from the host 102.In accordance with an embodiment, the processor 134 may use or executefirmware to control the overall operations of the memory system 110.Herein, the firmware may be a flash translation layer (FTL). The FTL mayserve as an interface between the host 102 and the memory device 150.The host 102 may transmit requests for write and read operations to thememory device 150 through the FTL.

According to an embodiment, the processor 134 and the memory interface142 may be used to perform an operation of the operation controlcircuitry 196, which is described above with reference to FIG. 1A.According to another embodiment, the processor 134 and the memoryinterface 142 may be used to perform an operation of the correlationcircuitry 194, which is described above with reference to FIG. 1A.According to another embodiment, the processor 134 and the memoryinterface 142 may be used to perform an operation of the pending creditdetermining circuitry 195, which is described above with reference toFIG. 1A. According to another embodiment, the processor 134 and thememory interface 142 may be used to perform an operation of themonitoring circuitry 197, which is described above with reference toFIG. 1A. According to another embodiment, the processor 134 and thememory interface 142 may be used to perform an operation of the readmode selection circuitry 199, which is described above with reference toFIG. 1A.

The FTL may manage operations of address mapping, garbage collection,wear-leveling and so forth. Particularly, the FTL may load, generate,update, or store map data. Therefore, the controller 130 may map alogical address, which is entered from the host 102, with a physicaladdress of the memory device 150 through the map data. The memory device150 may function as a general storage device to perform a read or writeoperation. Also, through the address mapping operation based on the mapdata, when the controller 130 tries to update data stored in aparticular page, the controller 130 may program the updated data onanother empty page and may invalidate old data of the particular page(e.g., update a physical address, corresponding to a logical address ofthe updated data, from the particular page to the newly programed page)due to a characteristic of a flash memory device. Further, thecontroller 130 may store map data of the new data into the FTL.

For example, when performing an operation requested from the host 102 inthe memory device 150, the controller 130 uses the processor 134. Theprocessor 134 engaged with the memory device 150 may handle instructionsor commands corresponding to an inputted command from the host 102. Thecontroller 130 may perform a foreground operation as a commandoperation, corresponding to a command from the host 102, such as aprogram operation corresponding to a write command, a read operationcorresponding to a read command, an erase/discard operationcorresponding to an erase/discard command and a parameter set operationcorresponding to a set parameter command or a set feature command with aset command.

The controller 130 may perform a background operation on the memorydevice 150 through the processor 134. By way of example but notlimitation, the background operation for the memory device 150 includescopying data in a memory block, among the memory blocks 152, 154, 156,and storing such data in another memory block (e.g., a garbagecollection (GC) operation). The background operation may include anoperation to move data stored in at least one of the memory blocks 152,154, 156 in the memory device 150 into at least another of the memoryblocks 152, 154, 156 (e.g., a wear leveling (WL) operation). During abackground operation, the controller 130 may use the processor 134 forstoring the map data stored in the controller 130 to at least one of thememory blocks 152, 154, 156, e.g., a map flush operation. A bad blockmanagement operation of checking for bad blocks among the plurality ofmemory blocks 152, 154, 156 is another example of a background operationperformed by the processor 134.

In the memory system 110, the controller 130 performs a plurality ofcommand operations corresponding to a plurality of commands receivedfrom the host 102. For example, when performing a plurality of programoperations corresponding to plural program commands, a plurality of readoperations corresponding to plural read commands and a plurality oferase operations corresponding to plural erase commands sequentially,randomly or alternatively, the controller 130 may determine whichchannel(s) or way(s) for connecting the controller 130 to which memorydie(s) in the memory 150 is/are proper or appropriate for performingeach operation. The controller 130 may transmit data or instructions viathe channel(s) or way(s) for performing each operation. The plurality ofmemory dies may transmit an operation result via the same channel(s) orway(s), respectively, after each operation is complete. Then, thecontroller 130 may transmit a response or an acknowledge signal to thehost 102. In an embodiment, the controller 130 may check a status ofeach channel or each way. In response to a command received from thehost 102, the controller 130 may select at least one channel or waybased on the status of each channel or each way so that instructionsand/or operation results with data may be delivered via selectedchannel(s) or way(s).

The controller 130 may check the states of a plurality of channels (orways) coupled to a plurality of memory dies that are included in thememory device 150. According to an embodiment, the controller 130 maycheck the states of a plurality of channels (or ways) coupled to aplurality of memory dies through the monitoring circuitry 197, which isdescribed above with reference to FIG. 1A.

By way of example but not limitation, the controller 130 may recognizestatuses regarding channels (or ways) associated with memory dies in thememory device 150. The controller 130 may determine each channel or eachway as being in a busy state, a ready state, an active state, an idlestate, a normal state, or an abnormal state. The controller'sdetermination of which channel or way an instruction (and/or a data) isdelivered through can be based on a physical block address, e.g., towhich die(s) the instruction (and/or the data) is delivered. Thecontroller 130 may refer to descriptors delivered from the memory device150. The descriptors may include a block or page of parameters thatdescribe characteristics of the memory device 150, and may have a setformat or structure. The descriptors may include device descriptors,configuration descriptors, unit descriptors, and the like. Thecontroller 130 can refer to, or use, the descriptors to determine withwhich channel(s) or way(s) an instruction or a data is exchanged.

A management unit (not shown) may be included in the processor 134. Themanagement unit may perform bad block management of the memory device150. The management unit may find bad memory blocks, which are inunsatisfactory condition for further use, as well as perform bad blockmanagement on the bad memory blocks. When the memory device 150 is aflash memory such as a NAND flash memory, a program failure may occurduring the write operation, for example, during the program operation,due to characteristics of a NAND logic function. During the bad blockmanagement, the data of the program-failed memory block or the badmemory block may be programmed into a new memory block. The bad blocksmay substantially reduce the utilization efficiency of the memory device150 having a 3D stack structure and the reliability of the memory system110. Thus, reliable bad block management may enhance or improveperformance of the memory system 110.

FIG. 3 is a block diagram illustrating a controller in a memory systemin accordance with another embodiment of the present disclosure.

Referring to FIG. 3, the controller 130 cooperates with the host 102 andthe memory device 150. The controller 130 may include a host interface(I/F) 132, flash translation layer (FTL) circuitry 40, a memoryinterface (I/F) 142 and a memory 144.

Although not shown in FIG. 3, in accordance with an embodiment, the ECCcircuitry 138 in FIG. 2 may be included in the flash translation layer(FTL) circuitry 40. In another embodiment, the ECC circuitry 138 may beimplemented as a separate module, a circuit, or firmware, which isincluded in, or associated with, the controller 130.

Also, according to an embodiment, the flash translation layer (FTL)circuitry 40 and the memory interface 142 may serve as the correlationcircuitry 194, which is described above with reference to FIG. 1.According to another embodiment, the flash translation layer (FTL)circuitry 40 and the memory interface 142 may serve as the pendingcredit determining circuitry 195, which is described above withreference to FIG. 1. According to another embodiment, the flashtranslation layer (FTL) circuitry 40 and the memory interface 142 mayserve as the monitoring circuitry 197, which is described above withreference to FIG. 1. According to another embodiment, the flashtranslation layer (FTL) circuitry 40 and the memory interface 142 mayserve as the read mode selection circuitry 199, which is described abovewith reference to FIG. 1.

The host interface 132 may handle commands and data from the host 102.By way of example but not limitation, the host interface 132 may includea command queue 56, a buffer manager 52 and an event queue 54. Thecommand queue 56 may sequentially store commands and data from the host102 and output them to the buffer manager 52 in a stored order. Thebuffer manager 52 may classify, manage or adjust commands and data whichare delivered from the command queue 56. The event queue 54 maysequentially transmit events for processing the commands and the data,from the buffer manager 52.

A plurality of commands or data having the same characteristics may besequentially received from the host 102, or commands and data havingdifferent characteristics may be transmitted to the memory system 110after being mixed. For example, a plurality of read commands may bedelivered, or read commands and program/write commands may bealternately transmitted to the memory system 110. The host interface 132may sequentially store commands and data, which are received from thehost 102, to the command queue 56. Thereafter, the host interface 132may estimate or predict what kind of internal operation the controller130 will perform according to the characteristics of the command anddata which is received from the host 102. The host interface 132 maydetermine a processing order and a priority of commands and data, basedat least on their characteristics. According to characteristics ofcommands and data, from the host 102, the buffer manager 52 in the hostinterface 132 is configured to determine whether the buffer manager 52should store commands and data in the memory 144, or whether the buffermanager 52 should deliver the commands and the data into the flashtranslation layer (FTL) circuitry 40. The event queue 54 receivesevents, entered from the buffer manager 52, which are to be internallyexecuted and processed by the memory system 110 or the controller 130 inresponse to the commands and the data from the host 102, so as todeliver the events into the flash translation layer (FTL) circuitry 40in the order received.

In accordance with an embodiment, the host interface 132 in FIG. 3 mayperform the functions of the controller 130 in FIG. 2.

In accordance with an embodiment, the flash translation layer (FTL)circuitry 40 may include a state manager (GC/WL) 42, a map manager (MM)44, a host request manager (HRM) 46, and a block manager (BM/BBM) 48.The host request manager 46 may manage the events entered from the eventqueue 54. The map manager 44 may handle or control map data. The statemanager 42 may perform garbage collection (GC) or wear leveling (WL).The block manager 48 may execute commands or instructions onto a blockin the memory device 150.

By way of example but not limitation, the host request manager 46 mayuse the map manager 44 and the block manager 48 to handle or processrequests according to the read and program commands, and events whichare delivered from the host interface 132. The host request manager 46may send an inquiry request to the map data manager 44, to determine aphysical address corresponding to the logical address which is enteredwith the events. The host request manager 46 may send a read requestwith the physical address to the memory interface 142, to process theread request (handle the events). On the other hand, the host requestmanager 46 may send a program request (or write request) to the blockmanager 48, to program entered data to an empty page (i.e., a pagehaving no data) in the memory device 150, and then, may transmit a mapupdate request corresponding to the program request to the map manager44, to update mapping addresses.

The block manager 48 may convert a program request delivered from thehost request manager 46, the map data manager 44, and/or the statemanager 42 into a flash program request used for the memory device 150,to manage flash blocks in the memory device 150. In order to maximize orenhance program or write performance of the memory system 110 (see FIG.2), the block manager 48 may collect program requests and send flashprogram requests for multiple-plane and one-shot program operations tothe memory interface 142. The block manager 48 may send several flashprogram requests to the memory interface 142 to enhance or maximizeparallel processing of the multi-channel and multi-directional flashcontroller.

The block manager 48 may be configured to manage blocks in the memorydevice 150 according to the number of valid pages, select and eraseblocks having no valid pages when a free block is needed, and select ablock including the least number of valid pages when it is determinedthat garbage collection is necessary. The state manager 42 may performgarbage collection to move the valid data to an empty block and eraseremaining data in the blocks from which the valid data was moved so thatthe block manager 48 may have enough free blocks. If the block manager48 provides information regarding a block to be erased to the statemanager 42, the state manager 42 is able to check all flash pages of theblock to be erased to determine whether each page is valid. To determinevalidity of each page, the state manager 42 may identify a logicaladdress stored in an out-of-band (OOB) area of each page. To determinewhether each page is valid, the state manager 42 may compare thephysical address of the page with the physical address mapped to thelogical address obtained from the request. The state manager 42 sends aprogram request to the block manager 48 for each valid page. A mappingtable may be updated through the update of the map manager 44 when theprogram operation is complete.

The map manager 44 may manage a logical-physical mapping table. The mapmanager 44 may process requests such as queries and updates, which aregenerated by the host request manager 46 or the state manager 42. Themap manager 44 may store the entire mapping table in the memory device150 (e.g., a flash/non-volatile memory) and cache mapping entriesaccording to the storage capacity of the memory 144. When a map cachemiss occurs while processing inquiry or update requests, the map manager44 may send a read request to the memory interface 142 to load arelevant mapping table stored in the memory device 150. When the numberof dirty cache blocks in the map manager 44 exceeds a certain threshold,a program request may be sent to the block manager 48 so that a cleancache block is made and the dirty map table may be stored in the memorydevice 150.

When garbage collection is performed, the state manager 42 copies validpage(s) into a free block, and the host request manager 46 may programthe latest version of the data for the same logical address of the pageand issue an update request. When the state manager 42 requests the mapupdate in a state in which copying of valid page(s) has not beencompleted, the map manager 44 may not perform the mapping table update.This is because the map request is issued with old physical informationif the state manger 42 requests a map update and a valid page copy isnot completed until later. The map manager 44 may perform a map updateoperation to ensure accuracy only if the latest map table still pointsto an old physical address.

The memory device 150 may include a plurality of memory blocks. Each ofthe plurality of memory blocks may be a single level cell (SLC) memoryblock or a multi level cell (MLC) memory block, according to the numberof bits that can be stored or represented in one memory cell of suchblock. Here, the SLC memory block includes a plurality of pagesimplemented by memory cells, each storing one bit of data. The SLCmemory block can have high data I/O operation performance and highdurability. The MLC memory block includes a plurality of pagesimplemented by memory cells, each storing multi-bit data (e.g., two bitsor more). The MLC memory block can have a larger storage capacity forthe same space compared to the SLC memory block. The MLC memory blockcan be highly integrated in terms of storage capacity. In an embodiment,the memory device 150 may be implemented with MLC memory blocks, such asa double level cell memory block, a triple level cell (TLC) memoryblock, a quadruple level cell (QLC) memory block and a combinationthereof. The double level memory block may include a plurality of pagesimplemented by memory cells, each capable of storing 2-bit data. Thetriple level cell (TLC) memory block may include a plurality of pagesimplemented by memory cells, each capable of storing 3-bit data. Thequadruple level cell (QLC) memory block may include a plurality of pagesimplemented by memory cells, each capable of storing 4-bit data. Inanother embodiment, the memory device 150 may be implemented with ablock including a plurality of pages implemented by memory cells, eachcapable of storing 5 or more bits of data.

In an embodiment of the disclosure, the memory device 150 is anonvolatile memory such as a flash memory such as a NAND flash memory, aNOR flash memory and the like. In another embodiment, the memory device150 may be at least one of a phase change random access memory (PCRAM),a ferroelectric random access memory (FRAM) and a spin injectionmagnetic memory (e.g., a spin transfer torque magnetic random accessmemory (STT-MRAM)).

FIG. 4 is a block diagram illustrating an internal structure of a memorydevice. More specifically, FIG. 4 illustrates an internal configurationof the memory device 150.

Referring to FIG. 4, the memory device 150 may include the plurality ofmemory dies 240A, 240B, 240C, 240D. The first memory die 240A and thesecond memory die 240B may be connected to the controller 130 (see FIGS.1 through 3) through the first channel CH #1. The third memory die 240Cand the fourth memory die 240D may be connected to the controller 130through the second channel CH #2.

FIG. 4 shows a configuration in which four memory dies 240A, 240B, 240C,240D are coupled to the controller 130 through two channels CH #1, CH#2. However, embodiments are not limited that or any particularconfiguration of dies and channels. Even though the memory device 150may include at least two dies and at least two channels, the number ofdies and channels in a given configuration depends on various factors,such as the overall configuration of the memory system, the purpose(s)for which it is employed and the specification defining communicationbetween the memory system and the engaged host.

When a plurality of memory dies is connected to a single channel, eachmemory die may be coupled with the channel through different ways. InFIG. 4, the first memory die 240A and the second memory die 240B may becoupled with the first channel CH #1 through the first way W1 and thesecond way W2, respectively. The third memory die 240C and the fourthmemory die 240D may be coupled with the second channel CH #2 through thefirst way W1 and the second way W2, respectively. In this particularconfiguration, the number of ways is the same as the number of memorydies.

FIG. 5A and FIG. 5B illustrate characteristics of a correlationoperation performed by the controller. Specifically, the two graphs inFIG. 5A and FIG. 5B illustrate results obtained by performingcorrelation operations repeatedly as described below.

Referring to FIG. 5A, as the correlation circuitry 194 in the controller130 of FIG. 1 attempts to establish correlations for an increasingnumber of read requests, a probability of correlating such read requestsincreases as the number of read requests increase. For example, theprobability of finding a correlation within 20 read requests is greaterthan that of 5 read requests.

When there is no address limitation in a memory system, physicallocations in the memory device 150 corresponding to logical addressesdelivered with a few read requests may not be distributed. In this case,the number of read requests correlated by the correlation circuitry 194may be small. However, when a large number of read requests aretransmitted to the memory system 110, the probability that the readrequests are correlated is higher. For example, the probability ofcorrelation may be higher when the number of read requests is the secondreference value REF2 compared to when the number of read requests is thefirst reference value REF1, which is less than REF2.

Referring to FIG. 5B, when a plurality of read requests are sequentiallytransmitted to the correlation circuitry 194, the probability ofcorrelation according to an input time (or input sequence) of the readrequests is described. As described with reference to FIG. 4, it isassumed that there are two channels between the controller 130 and thememory device 150 in the memory system 110. For example, a first readrequest sent to the correlation circuitry 194 may not be correlatedbecause there are no other read requests which are ready to becorrelated. When a second read request is delivered to the correlationcircuitry 194, the second read request may or may not be correlated withthe base read request; the probability of such correlation is 50:50.When a third read request is delivered to the correlation circuitry 194,the correlation circuitry 194 may attempt to correlate the third readrequest with the previous read requests if they are not correlated.Thus, the probability of correlation may be higher when the third readrequest is delivered than when the second read request is delivered.Based on these characteristics, the correlation circuitry 194 maydetermine the correlation state, i.e., whether or not to attempt toperform a correlation operation, before and after a specific readrequest is received. For example, after a read request (corresponding tothird reference value REF3) is received, the correlation circuitry 194may determine that a probability of correlation is sufficiently high,and attempt to perform the correlation operation on thepreviously-received read request(s) together with the (REF3) readrequest. In contrast, before the (REF3) read request is received, thecorrelation circuitry 194 may determine that a probability ofcorrelation is too low, and thus skip performing the correlationoperation on the read requests received before the REF3 read request.

In another example, it is assumed that 20 read requests are delivered.When the 19th and 20th read requests are inputted, the probability ofcorrelation may be lower when the 9th to 11th read requests areinputted. This is because, when the 19th and 20th read requests areinputted, the previously inputted 1st to 18th read requests readrequests may have been already correlated and outputted to the operationcontrol circuitry 196. As the correlated read requests are transferredover time, the probability of correlation may be lowered. In order toavoid the correlation circuitry 194 wasting resources such as time,overhead, or power to perform the correlation operation, the correlationoperation may be stopped at a time when the read request correspondingto a fourth reference value REF4 is transmitted.

In an embodiment, the correlation circuitry 194 may stop the correlationoperation in response to a particular number of uncorrelated readrequests. For example, if a small number of uncorrelated read requests,e.g., two or three, remain, among the 20 read requests, the correlationcircuitry 194 may output the uncorrelated read requests to the operationcontrol circuitry 196 without holding them for a next correlationoperation. When the correlation circuitry 194 holds a few read requestsfor performing a next correlation operation, the data input/outputperformance (e.g., I/O throughput) of the memory system 110 may bedeteriorated.

As shown in FIG. 5B, if the correlation circuitry 194 determines whetherto perform a correlation operation using only the number of readrequests received from the I/O buffer control circuitry 198 as areference REF3 or REF4, the accuracy or efficiency of an operation ofdetermining whether to perform a correlation operation may be reduced.For example, if success of a correlation operation occurs morefrequently than a predicted probability, all read requests correspondingto a predicted number may be processed within a time shorter than apredicted time, and the correlation circuitry 194 may then enter an idlestate. In contrast, if failure of a correlation operation occurs morefrequently than a predicted probability, all read requests correspondingto a predicted number may not be processed within a predicted time, anddata I/O throughput may be adversely affected due to the delay of anoperation of the correlation circuitry 194. Furthermore, if success of acorrelation operation is repeated with respect to only specific memorydies of the multiple memory dies 240A, 240B, 240C, and 240D, theremaining memory dies that are not a target of the correlation operation(or on which the correlation operation has failed) may remain in an idlestate (although a corresponding read request is present) due to a policyfor preferentially processing a read request on which a correlationoperation has been successful.

In order to solve such a problem, when a candidate read request to betransmitted from the I/O buffer control circuitry 198 to the correlationcircuitry 194 is selected, the pending credit determining circuitry 195may check, from the correlation circuitry 194, whether a previouscorrelation operation has been performed by the correlation circuitry194 prior to selection timing at which the candidate read request isselected and whether an executed correlation operation is successful ifthe correlation operation has been performed, may identify the operatingstates of the multiple memory dies 240A, 240B, 240C, and 240D at theselection timing from the monitoring circuitry 197, may collect theresults of the identification, and then may convert the collectedresults into a numerical value called a pending credit. Next, thecorrelation circuitry 194 may determine whether to perform a correlationoperation on the candidate read request, selected and input at theselection timing, based on the pending credit determined at theselection timing.

FIG. 6 is a block diagram illustrating an internal structure of thecontroller.

Referring to FIG. 6, the controller 130 may include an input buffer 186,an output buffer 184, the I/O buffer control circuitry 198, thecorrelation circuitry 194, the pending credit determining circuitry 195,the monitoring circuitry 197, a map memory 182, the operation controlcircuitry 196, and the read mode selection circuitry 199. For example,the I/O buffer control circuitry 198, the correlation circuitry 194 andthe operation control circuitry 196 may determine the execution or stopof a correlation operation while operating in conjunction with theoutput buffer 186, the input buffer 184, the pending credit determiningcircuitry 195, the monitoring circuitry 197 and the map memory 182.Furthermore, the correlation circuitry 194, the operation controlcircuitry 196 and the pending credit determining circuitry 195 mayselect whether to read additional data related to target data whenreading the target data corresponding to a read request, while operatingin conjunction with the read mode selection circuitry 199.

In some embodiments, the output buffer 186, the input buffer 184 and themap memory 182 may be functionally separate components, and may beimplemented within the memory 144 described with reference to FIGS. 2and 3. Furthermore, in some embodiments, the output buffer 186, theinput buffer 184 and the map memory 182 may be implemented as multiplenon-volatile memory apparatuses or multiple cache memories.

For example, the output buffer 186 and the input buffer 184 may have adata structure, such as a queue. In this case, the output buffer 186 andthe input buffer 184 may output data in stored order (FIFO). The mapmemory 182 may have various structures depending on a storage ormanagement policy of map data or map information.

The controller 130 may translate a logical address, that is, an addressreceived from the host 102 (refer to FIGS. 2 and 3), into a physicaladdress indicative of a physical location within the memory apparatus150 (refer to FIGS. 1 to 4). For the address translation, the controller130 may load map data or map information stored in the memory apparatus150.

In some embodiments, if the storage space of the memory 144 (refer toFIGS. 2 and 3) included in the controller 130 or operating inconjunction with the controller 130 is sufficient, all map data or mapinformation used for address translation may be invoked at a time.However, in the case of the memory system 110 (refer to FIGS. 1 to 3)mounted on a portable terminal, etc., it may be difficult for thecontroller 130 to have a sufficient storage space capable of storing allmap data or map information. In this case, the controller 130 may use aspace for storing map data or map information within the memory 144 insuch a way to invoke specific map information from the memory apparatus150, use or update the specific map information, store the specific mapinformation in the memory apparatus 150, and invoke another piece of mapinformation stored in the memory apparatus 150.

If requested map data cannot be stored in a region within the memory144, the controller 130 may remove the least recently used map datawithin the region. Furthermore, for another example, if requested mapdata cannot be stored in a region within the memory 144, the controller130 may remove the least frequently used map data within the region. Thecontroller 130 may request map data or map information for addresstranslation from the memory apparatus 150, but this may be overhead foroverall performance or I/O throughput of the memory system 110.Accordingly, it is necessary to allow the controller 130 not to requestunnecessary map data or map information.

For example, it is assumed that the number of read requests input fromthe host 102 (refer to FIGS. 2 and 3) for correlation operation is 20.As a result of checking the map memory 182 based on a logical addressrelated to the 20 read requests, map data or map addresses for 11 readrequests may be present in the map memory 182, and map data or mapaddresses for 9 read requests may not be present in the map memory 182.In this case, the controller 130 may load the map data or map addressesfor the 9 read requests onto the map memory 182. In some embodiments, ifthe storage space of the map memory 182 is not sufficient, thecorrelation circuitry 194 may first perform a correlation operation on aread request whose map address can be identified.

The correlation operation performed by the correlation circuitry 194 maybe recognized as overhead from the point of view of I/O throughput ofthe memory system 110 (refer to FIGS. 1 to 3). Accordingly, it may bemore preferred to allow the operation control circuitry 196 to be in anactive state, rather than have the correlation circuitry 194 perform thecorrelation operation on all of transmitted read requests performed.

Accordingly, the correlation circuitry 194 may determine whether toperform a correlation operation on a candidate read request that isselected at selection timing and received from the I/O buffer controlcircuitry 198 based on a pending credit determined at the selectiontiming at which the I/O buffer control circuitry 198 selects thecandidate read request and the type of data corresponding to thecandidate read request. For example, if the data of a candidate readrequest selected by the I/O buffer control circuitry 198 is data forwhich read has been requested through an internal operation of thecontroller 130 or random read data requested by the host 102, when apending credit determined at selection timing at which the I/O buffercontrol circuitry 198 selects the candidate read request is a referencevalue or more, the correlation circuitry 194 may perform a correlationoperation on the candidate read request that is selected at theselection timing and received from the I/O buffer control circuitry 198.Furthermore, if the data of a candidate read request selected by the I/Obuffer control circuitry 198 is data that is read-requested through aninternal operation of the controller 130 or random data that isread-requested by the host 102, when a pending credit determined atselection timing at which the I/O buffer control circuitry 198 selectsthe candidate read request is less than a reference value, thecorrelation circuitry 194 may not perform a correlation operation on thecandidate read request that is selected at the selection timing andreceived from the I/O buffer control circuitry 198. Furthermore, if thedata of a candidate read request selected by the I/O buffer controlcircuitry 198 is sequential data that is read-requested by the host 102,the correlation circuitry 194 may not perform a correlation operation onthe candidate read request that is selected at selection timing andreceived from the I/O buffer control circuitry 198, regardless of avalue of a pending credit determined at the selection timing at whichthe I/O buffer control circuitry 198 selects the candidate read request.For reference, examples of data for which read has been requestedthrough an internal operation of the controller 130 includes map dataread from the memory apparatus 150 to the map memory 182, data read fromthe memory apparatus 150 for a garbage collection operation, data readfrom the memory apparatus 150 for a read reclaim operation, or data readfrom the memory apparatus 150 for a wear leveling operation.

In this case, the pending credit determining circuitry 195 may determinea pending credit by checking whether a previous correlation operationhas been performed by the correlation circuitry 194 prior to selectiontiming at which a candidate read request to be transmitted from the I/Obuffer control circuitry 198 to the correlation circuitry 194 isselected.

Specifically, the pending credit determining circuitry 195 may increasea pending credit in response to the processing of a candidate readrequest without a correlation operation prior to selection timing atwhich the I/O buffer control circuitry 198 selects the candidate readrequest. More specifically, the pending credit determining circuitry 195may increment a pending credit based on an expected processing time of acandidate read request processed without a correlation operation priorto selection timing at which the I/O buffer control circuitry 198selects the candidate read request. For example, if an expectedprocessing time of a candidate read request processed without acorrelation operation is 50 us, the pending credit determining circuitry195 may determine a pending credit by increasing the current pendingcredit by 5. Furthermore, if an expected processing time of a candidateread request processed without a correlation operation is 10 us, thepending credit determining circuitry 195 may determine a pending creditby increasing the current pending credit by 1. For reference, a casewhere a candidate read request is processed without a correlationoperation may be a case where a pending credit determined by the pendingcredit determining circuitry 195 is less than a reference value atselection timing at which the I/O buffer control circuitry 198 selectsthe candidate read request. Furthermore, two different read requests mayhave different expected processing times due to circumstances, e.g.,because the sizes of data to be read from the memory apparatus 150 inresponse to the read requests are different. In this case, the expectedprocessing time corresponding to the read request can also be predictedbecause the size of the data read from the memory apparatus 150 inresponse to the read request is known. An expected processing timecorresponding to a read request may be different depending on the typeor throughput of the memory apparatus 150.

Furthermore, after a previous correlation operation is performed priorto selection timing at which a candidate read request to be transmittedfrom the I/O buffer control circuitry 198 to the correlation circuitry194 is selected, the pending credit determining circuitry 195 maydetermine a pending credit by checking, from the correlation circuitry194, whether the executed correlation operation has been successful.

Specifically, the pending credit determining circuitry 195 may increasethe pending credit based on the success of the previous correlationoperation executed by the correlation circuitry 194 prior to theselection timing at which the I/O buffer control circuitry 198 selectsthe candidate read request, and may decrease the pending credit based onthe failure of the correlation operation. More specifically, the pendingcredit determining circuitry 195 may increment the pending credit basedon the time expected to be shortened due to the success of the previouscorrelation operation executed by the correlation circuitry 194 prior tothe selection timing at which the I/O buffer control circuitry 198selects the candidate read request. Furthermore, the pending creditdetermining circuitry 195 may decrement the pending credit based on thetime consumed due to the failure of the previous correlation operationexecuted by the correlation circuitry 194 prior to the selection timingat which the I/O buffer control circuitry 198 selects the candidate readrequest. For example, if the time expected to be shortened due to thesuccess of the correlation operation executed by the correlationcircuitry 194 is 30 us, the pending credit determining circuitry 195 maydetermine the pending credit by increasing the current pending credit by3. Furthermore, if the time consumed due to the failure of thecorrelation operation executed by the correlation circuitry 194 is 20us, the pending credit determining circuitry 195 may determine thepending credit by decreasing the current pending credit by 2. Forreference, the reason why the time can be reduced due to the success ofa correlation operation is that, if the correlation operation issuccessful, at least two read requests can be processed at a time in aninterleaving manner and less time is used compared to a case where theat least two read requests are independently processed without acorrelation operation. That is, a difference between the time expectedto be used to process at least two read requests independently without acorrelation operation and the time expected to be used to process atleast two read operations in an interleaving manner as a result of asuccessful correlation operation may be the time saved due to thesuccess of the correlation operation. Furthermore, if the correlationoperation has failed, time is used to check the failure of thecorrelation operation after the correlation operation is performed, butas a result, a read request is processed the same as when thecorrelation operation is not performed. That is, the time taken toperform a failed correlation operation represents additional time in theprocessing of that read request.

Furthermore, the pending credit determining circuitry 195 may determinea pending credit by identifying, from the monitoring circuitry 197, theoperating states of the multiple memory dies 240A, 240B, 240C, and 240Dat selection timing at which a candidate read request to be transmittedfrom the I/O buffer control circuitry 198 to the correlation circuitry194 is selected.

Specifically, the pending credit determining circuitry 195 may decreasea pending credit when at least one of the multiple memory dies 240A,240B, 240C, and 240D is an idle state at selection timing at which theI/O buffer control circuitry 198 selects a candidate read request. Morespecifically, the pending credit determining circuitry 195 may decrementthe pending credit based on the number of memory dies that are in theidle state at the selection timing at which the I/O buffer controlcircuitry 198 selects the candidate read request. For example, if thenumber of memory dies in the idle state at the selection timing is 1,the pending credit determining circuitry 195 may determine the pendingcredit by decreasing the current pending credit by 2. Furthermore, ifthe number of memory dies in the idle state at the selection timing is2, the pending credit determining circuitry 195 may determine thepending credit by decreasing the current pending credit by 4.

Furthermore, after the correlation circuitry 194 determines whether toperform a correlation operation based on a pending credit at selectiontiming at which the I/O buffer control circuitry 198 selects a candidateread request, if the I/O buffer control circuitry 198 does not selectthe candidate read request for a reference time or more, the pendingcredit determining circuitry 195 may reset the pending credit to aninitial value. That is, if a correlation operation performed by thecorrelation circuitry 194 is not sequential for a reference time ormore, the pending credit determining circuitry 195 may reset a pendingcredit to an initial value. In this case, the initial value of thepending credit may be smaller than a reference value of the pendingcredit that is used as a reference when the correlation circuitry 194determines whether to perform a correlation operation. For reference,the reference time may be set such that it represents the time betweentwo read requests that are determined to be not sequential to eachother. For example, the reference time may be the time consumed until aread request is transmitted to multiple memory dies and the processingof the read request is completed after a correlation operation issuccessfully performed on the read request.

Separately from a correlation operation performed by the correlationcircuitry 194, the controller 130 may read, from the multiple memorydies 240A, 240B, 240C, and 240D, target data corresponding to a readrequest and additional data stored in the same storage unit as thetarget data, based on the type of target data corresponding to the readrequest and a pending credit determined by the pending creditdetermining circuitry 195. That is, separately from the execution of acorrelation operation, on at least some candidate read requests of aplurality of base read requests received from the host or generatedwithin the controller through the correlation circuitry 194, thecontroller 130 may perform an operation of reading, from the multiplememory dies 240A, 240B, 240C, and 240D, target data corresponding to thecandidate read requests and additional data stored in the same storageunit as the target data through the read mode selection circuitry 199.

In this case, as illustrated in FIG. 1B, each of the multiple memorydies 240A, 240B, 240C, and 240D may include the pages PAGE0, PAGE1,PAGE2, . . . each including a set number of sections, e.g., SECTION0,SECTION1, SECTION2, and SECTION3, the multiple blocks BLOCK000,BLOCK001, BLOCK002, . . . , BLOCK010, BLOCK011, BLOCK012, . . . eachincluding the pages PAGE0, PAGE1, PAGE2, . . . , and the page buffersPB000, PB001, PB002, . . . , PB010, PB011, PB012, . . . for caching datainput to or output from the blocks in certain units. That is, each ofthe multiple memory dies 240A, 240B, 240C, and 240D may output datacached in the page buffers PB000, PB001, PB002, . . . , PB010, PB011,PB012, . . . , in units of sections or in units of pages in response toa read request.

Accordingly, if a candidate read request is directed to data in asection, when the controller 130 processes the candidate read request,the controller 130 may read, from the multiple memory dies 240A, 240B,240C, and 240D, target data stored in a requested section correspondingto the candidate read request and may also read additional data storedin the same page as the target data together, based on the type oftarget data corresponding to the candidate read request and a pendingcredit determined by the pending credit determining circuitry 195 at theprocessing timing of the candidate read request. In this case, the typeof target data may indicate whether the target data is sequential datathat is read-requested through an internal operation of the controller130, random data that is read-requested through an internal operation ofthe controller 130 or data that is read-requested by the host 102.

Specifically, if a candidate read request is a read request of a sectionunit through the read mode selection circuitry 199 and target datacorresponding to the candidate read request is sequential data for whichread has been requested through an internal operation of the controller130, when a pending credit determined by the pending credit determiningcircuitry 195 at processing timing at which the candidate read requestis a reference value or more, the controller 130 may read, from themultiple memory dies 240A, 240B, 240C, and 240D, the target datacorresponding to the candidate read request and additional data storedin the same page as the target data together. Furthermore, if acandidate read request is a read request of a section unit through theread mode selection circuitry 199 and target data corresponding to thecandidate read request is sequential data for which read has beenrequested through an internal operation of the controller 130, when apending credit determined by the pending credit determining circuitry195 at processing timing at which the candidate read request is lessthan a reference value, the controller 130 may select only the targetdata corresponding to the candidate read request, and may read theselected target data from the multiple memory dies 240A, 240B, 240C, and240D (a second read mode CASE2). Furthermore, if a candidate readrequest is a read request of a section unit through the read modeselection circuitry 199 and target data corresponding to the candidateread request is random data for which read has been requested through aninternal operation of the controller 130 or data that is read-requestedby the host, the controller 130 may select only the target datacorresponding to the candidate read request regardless of a pendingcredit determined by the pending credit determining circuitry 195, andmay read the selected target data from the multiple memory dies 240A,240B, 240C, and 240D (a first read mode CASE1). The first and secondread modes CASE1 and CASE2 are described in more detail with referenceto FIG. 10.

Furthermore, a pending credit reference value of the pending creditdetermining circuitry 195, that is, a criterion by which the correlationcircuitry 194 determines whether to perform a correlation operation on aread request, and a pending credit reference value of the pending creditdetermining circuitry 195, that is, a criterion by which the read modeselection circuitry 199 determines whether to read additional data alongwith target data corresponding to a read request, may be different. Forexample, assuming that a pending credit reference value of the pendingcredit determining circuitry 195, that is, a criterion by which the readmode selection circuitry 199 determines whether to read additional dataalong with target data corresponding to a read request, is a firstreference value and a pending credit reference value of the pendingcredit determining circuitry 195, that is, a criterion by which thecorrelation circuitry 194 determines whether to perform a correlationoperation on a read request, is a second reference value, the firstreference value and the second reference value may be equal ordifferent. Furthermore, the first reference value may be greater orsmaller than the second reference value. In this case, as in theaforementioned description, it is assumed that the read mode selectioncircuitry 199 selects a read mode with respect to a read requesttransmitted from the correlation circuitry 194 to the operation controlcircuitry 196 when an operation margin is sufficient to the extent thatthe correlation circuitry 194 can smoothly perform a correlationoperation. Accordingly, the first reference value may be equal to orgreater than the second reference value.

FIGS. 7 to 9 are flowcharts describing a first example of a method foroperating a memory system.

First, referring to FIG. 7, the operating method may include theexecution and determination steps S10, S20, S30, S40, and S45 ofperforming a correlation operation on a read request so that themultiple memory dies 240A, 240B, 240C, and 240D (refer to FIG. 1)interleave and output data corresponding to the read request throughmultiple channels and determining a pending credit into which theresults of the correlation operation have been incorporated and theselection and read step S50 of reading, from the multiple memory dies,target data corresponding to the read request and additional data storedin the same storage unit as the target data based on the type of targetdata corresponding to the read request and the pending credit. In thiscase, the execution and determination steps S10, S20, S30, S40, and S45may include the selection step S10 of selecting, as a target of acorrelation operation, at least some candidate read requests among aplurality of base read requests, the determination step S20 ofdetermining a pending credit based on whether a previous correlationoperation has been performed prior to selection timing at which thecandidate read request is selected in the selection step S10, whetherthe previous correlation operation was successful prior to the selectiontiming, and operating states of the multiple memory dies at theselection timing, the execution step S30 of determining whether toperform a correlation operation on the candidate read request selectedat the selection timing at the selection step S10 based on the type ofdata of the candidate read request selected at the selection timing atthe selection step S10 and the pending credit determined in thedetermination step S20, and the reset steps S40 and S45 of resetting thepending credit to an initial value when a candidate read request is notselected in the selection step S10 for a reference time or more afterwhether to perform the correlation operation is determined in theexecution step S30. In this case, the reset steps S40 and S45 mayinclude the check step S40 of checking whether the candidate readrequest has been selected in the selection step S10 for the referencetime or more after whether to perform the correlation operation isdetermined in the execution step S30 and the step (YES or NO) ofselecting whether to reset the pending credit based on a result of thecheck step S40. That is, if the result of the check step S40 (YES)indicates that the candidate read request is not selected for thereference time or more, the pending credit may be reset (S45).

After the reset S45 of the pending credit, the execution anddetermination steps S10, S20, S30, S40, and S45 may be repeatedlyperformed while the selection step S10 of selecting a candidate readrequest again is performed. In contrast, if the result of the check stepS40 (NO) indicates that the candidate read request is selected withinthe reference time, this corresponds to a case where the selection stepS10 is performed within the reference time after the check step S40, andthus the selection step S10 may be performed after the check step S40.In this case, an initial value of the pending credit may be smaller thana reference value of the pending credit, that is, a criterion fordetermining whether to perform a correlation operation in thedetermination step S20. That is, after the pending credit is reset to aninitial value through the reset steps S40 and S45, a candidate readrequest first selected in the selection step S10 will not be correlatedin the execution step S30 because the pending credit of the candidateread request starts from an initial value.

Furthermore, as illustrated in FIG. 1B, it may be assumed that each ofthe multiple memory dies 240A, 240B, 240C, and 240D includes the pagesPAGE0, PAGE1, PAGE2, . . . each including the sections SECTION0,SECTION1, SECTION2, and SECTION3 corresponding to a set number, themultiple blocks BLOCK000, BLOCK001, BLOCK002, . . . , BLOCK010,BLOCK011, BLOCK012, . . . each including the pages PAGE0, PAGE1, PAGE2,. . . , and the page buffers PB000, PB001, PB002, . . . , PB010, PB011,PB012, . . . for caching data input to or output from the blocksBLOCK000, BLOCK001, BLOCK002, . . . , BLOCK010, BLOCK011, BLOCK012, . .. in page units.

In such a case, in the selection and read step S50, if the candidateread request selected in the selection step S10 is a read request of asection unit, the data of a page including a requested sectioncorresponding to the candidate read request may be read in a page unitbased on the type of data of a processed candidate read request when thecandidate read request is processed and a pending credit at theprocessing timing of the processed candidate read request. In this case,the selection and read step S50 may not be directly associated with theexecution and determination steps S10, S20, S30, S40, and S45, exceptthat the selection and read step S50 operates based on a pending creditand starts to operate again when another candidate read request isselected in the selection step S10 after the operation. Accordingly, theremaining operations S30, S40, and S45 of the execution anddetermination steps S10, S20, S30, S40, and S45 except the selectionstep S10 and the determination step S20 may not be directly associatedwith the operation of the selection and read step S50.

Specifically, referring to FIG. 8, the selection and read step S50 mayinclude the data identification step S51 of identifying the type of dataof a processed candidate read request when the candidate read request isprocessed if the candidate read request selected in the selection stepS10 is a read request of a section unit, the reference check step S52 ofchecking whether a pending credit at timing at which the candidate readrequest is processed is a reference value or more if the data of theprocessed candidate read request is identified in the dataidentification step S51 as sequential data that is read-requestedthrough an internal operation of the controller 130 (S51_1), the firstread step S53 of reading the data of a page, including a requestedsection corresponding to the candidate read request, in a page unit ifthe result of the reference check step S52 (YES) indicates that thepending credit at the timing at which the candidate read request isprocessed is the reference value or more, and the second read step S54of selecting and reading only the data of a requested sectioncorresponding to the candidate read request when the data of theprocessed candidate read request is identified in the dataidentification step S51 as random data that is read-requested through aninternal operation of the controller 130 or data that is read-requestedby the host 102 (S51_2) or the result of the reference check step S52(NO) indicates that the pending credit at the timing at which thecandidate read request is processed is less than the reference value.

Although not directly illustrated in this drawing, if a correlationoperation is performed on the candidate read request, selected in theselection step S10, in the execution step S30, the operating method ofthe memory system may further include the first transmission step ofidentifying a target address for a read request correlated based on thesuccess of the correlation operation and then transmitting the readrequest to the multiple memory dies through multiple channels, the firstreception step of receiving the data of the correlated read request inan interleaving manner through the multiple channels after the firsttransmission step, the second transmission step of identifying a targetaddress for a read request not correlated due to the failure of thecorrelation operation and then transmitting the read request to themultiple memory dies, the second reception step of reading datacorresponding to the non-correlated read request from the multiplememory dies after the second transmission step, and the step ofoutputting, to a host, the data received in the first or secondreception step. In this case, I/O throughput of the memory system 110can be improved by transmitting the read request, correlated in thefirst transmission step, to the multiple memory dies earlier than theread request not correlated in the second transmission step.

In the selection step S10, reference may be made to the number of baseread requests received from a host, an operating state of the outputbuffer, etc. That is, in order to perform a correlation operation withina range in which I/O throughput of the memory system does notdeteriorate, a candidate read request may be selected as a correlationoperation target after an operation margin for the correlation operationis secured.

For example, for the selection step S10, whether the number of pieces ofdata that are to be output from the output buffer to a host is greaterthan a reference number may be determined. In this case, the referencenumber may be determined to correspond to a first data I/O speed betweenthe host and the memory system and a second data I/O speed between thecontroller and the multiple memory dies. For example, it is assumed thatthe time taken for the memory system to transmit one piece of data to ahost is 10 ms. If 10 pieces of data to be output to are included in theoutput buffer, the memory system may have an operation margin of 100 ms(=10×10). For example, assuming that the time taken for a read requestto be transmitted and data to be received between the controller andmemory apparatus of the memory system is 5 ms, the controller mayattempt correlation operation for a maximum of 95 ms of the 100 msoperation margin.

The controller of the memory system may be aware of an operation speedof and required time for an internal operation, and may compute anoperation margin according to a protocol with the host operating inconjunction with the memory system. Accordingly, the controller maycompute and estimate an operation margin on which correlation operationmay be attempted. For example, the controller may compute a maximumvalue of an operation margin for correlation operation, and then performthe correlation operation for a time corresponding to 70 to 90% of themaximum value. In some embodiments, a time category on which thecontroller may attempt correlation operation may be different.Furthermore, the controller may determine an operation margin, on whichcorrelation operation may be attempted, in accordance with an operatingenvironment of the memory system, an operating state of the memoryapparatus, etc.

Specifically, in the determination step S20, the pending credit may bedetermined at selection timing at which the candidate read request isselected in the selection step S10. More specifically, referring to FIG.9, the determination step S20 may include the first identification stepS22 of identifying whether the state of at least one of the multiplememory dies is an idle state at selection timing at which the candidateread request is selected in the selection step S10, the secondidentification step S28 of checking whether a previous correlationoperation has failed prior to the selection timing at which thecandidate read request is selected in the selection step S10, the thirdcheck step S24 of checking whether the candidate read request has beenprocessed without a correlation operation prior to the selection timingat which the candidate read request is selected in the selection stepS10, the fourth check step S26 of checking whether a previouscorrelation operation has been successful prior to the selection timingat which the candidate read request is selected in the selection stepS10, the step S27 of decreasing a pending credit if the result of thefirst identification step S22 (YES) indicates that the state of at leastone memory die is the idle state or if the result of the secondidentification step S28 (YES) indicates a previous correlation operationhas failed prior to the selection timing at which the candidate readrequest is selected in the selection step S10, and the step S29 ofincreasing a pending credit if the result of the third identificationstep S24 (YES) indicates that the candidate read request is processedwithout a correlation operation prior to the selection timing at whichthe candidate read request is selected in the selection step S10, or ifthe result of the fourth check step S26 (YES) indicates that a previouscorrelation operation has been successful prior to the selection timingat which the candidate read request is selected in the selection stepS10. In this case, if the result of the first identification step S22(NO) indicates that the states of none of the multiple memory dies arethe idle state (NO) or if the result of the second identification stepS28 (NO) indicates that the previous correlation operation has beensuccessful prior to the selection timing at which the candidate readrequest is selected in the selection step S10, the operation of the stepS27 of decreasing the pending credit may not be performed. Likewise, ifthe result of the third identification step S24 (YES) indicates that thecandidate read request has not been processed without a correlationoperation prior to the selection timing at which the candidate readrequest is selected in the selection step S10 or if the result of thefourth check step S26 (NO) indicates that a previous correlationoperation has failed prior to the selection timing at which thecandidate read request is selected in the selection step S10, theoperation of the step S29 of increasing the pending credit may not beperformed.

In this case, in the determination step S20, the step S27 of decreasingthe pending credit and the step S29 of increasing the pending credit mayoperate in parallel. For example, if at least one memory die is in theidle state at the selection timing at which the candidate read requestis selected in the selection step S10 and a previous correlationoperation was successful prior to the selection timing, the operationsof the first identification step S22 and the step S28 of decreasing thepending credit and the operations of the fourth check step S26 and thestep S29 of increasing the pending credit may operate in parallel and apending credit may be determined.

In this case, in the first identification step S22 and the step S27 ofdecreasing the pending credit, the pending credit may be decrementedbased on the number of memory dies that are in an idle state at theselection timing at which the candidate read request is selected in theselection step S10. That is, the more dies that are in the idle state atthe time that the candidate read request is selected in step S10, thegreater the pending credit is decreased. For example, the pending creditis decreased more when there are two dies in the idle state than whenthere is only one die in the idle state.

Furthermore, in the second identification step S28 and the step S27 ofdecreasing the pending credit, the pending credit may be decrementedbased on the time consumed due to the failure of a previous correlationoperation performed prior to the selection timing at which the candidateread request is selected in the selection step S10. That is, the pendingcredit may be decreased more as the time consumed due to the failure ofa previous correlation operation performed prior to the selection timingat which the candidate read request is selected in step S10 increases.

Furthermore, in the third check step S24 and the step S29 of increasingthe pending credit, the pending credit may be incremented based on anexpected processing time of a candidate read request processed without acorrelation operation prior to the selection timing at which thecandidate read request is selected in the selection step S10. That is,the pending credit may be increased more as the expected processing timeof a candidate read request processed without a correlation operationprior to the selection timing at which the candidate read request isselected increases.

Furthermore, in the fourth check step S26 and the step S29 of increasingthe pending credit, the pending credit may be increased based on anexpected shorter processing time due to the success of a previouscorrelation operation performed prior to the selection timing at whichthe candidate read request is selected in the selection step S10. Thatis, the pending credit may be increased more as expected processing timebecomes shorter due to the success of a previous correlation operationperformed prior to the selection timing at which the candidate readrequest is selected in the selection step S10.

In the execution step S30, whether to perform a correlation operation onthe candidate read request selected in the selection step S10 may bedetermined based on the pending credit determined in the determinationstep S20. Specifically, when the pending credit determined in thedetermination step S20 at the selection timing at which the candidateread request is selected in the selection step S10 is a reference valueor more, in the execution step S30, a correlation operation may beperformed on the candidate read request selected in the selection stepS10. In contrast, when the pending credit determined in thedetermination step S20 at the selection timing at which the candidateread request is selected in the selection step S10 is less than thereference value, in the execution step S30, a correlation operation maynot be performed on the candidate read request selected in the selectionstep S10.

FIG. 10 illustrates a first operation of the controller depending on thetype of data.

FIG. 10 is a diagram illustrating that the read mode selection circuitry199 selects a read mode CASE1 or CASE2 of the operation controlcircuitry 196 based on the type of data corresponding to a read requestreceived from the correlation circuitry 194.

Specifically, the type of data corresponding to the read requestreceived from the correlation circuitry 194 may include internal datagenerated through an internal operation of the controller 130 (InternalData) and host data received from the host 102 (Host Data).

In this case, if the read request corresponds to Host Data, the readmode selection circuitry 199 may control the operation control circuitry196 to select the first read mode CASE1. Furthermore, if Internal Datais sequential, the read mode selection circuitry 199 may control theoperation control circuitry 196 to select the second read mode CASE2.Furthermore, if Internal Data is random, the read mode selectioncircuitry 199 may control the operation control circuitry 196 to selectthe first read mode CASE1.

In this case, if Internal Data is sequential, this may mean thatsequential map data (Map-Cache Data (Sequential)) is generated andmanaged within the controller 130. Furthermore, if Internal Data issequential, this may mean that not much fragmented data is moved througha garbage collection operation within the controller 130.

In contrast, if Internal Data is random, this may mean thatnon-sequential random map data (Map-Cache Data (Random)) is generatedand managed within the controller 130. Furthermore, if Internal Data israndom, this may mean that very fragmented data is moved through agarbage collection operation within the controller 130.

For reference, an operation for the controller 130 to determine acharacteristic of Internal Data may be defined in advance and applied bythe controller 130 when data is generated.

In the first read mode CASE1, the operation control circuitry 196 mayselect and read only target data corresponding to a read request. Forexample, as illustrated in FIG. 10, if data stored in two sections Sec.0and Sec.1 of four sections Sec.0, Sec.1, Sec.2, and Sec.3 included inone page is target data corresponding to a read request, the first readmode CASE1 may be an operation of selecting and reading only target datastored in the two sections Sec.0 and Sec.1. In this case, in the firstread mode CASE1, the data stored in the two sections Sec.0 and Sec.1 ofthe four sections Sec.0, Sec.1, Sec.2, and Sec.3 included in the pagemay be cached in the page buffer and then read as the target data inresponse to the read request. In contrast, data stored in the remainingtwo sections Sec.2 and Sec.3 may be cached in the page buffer and not beread because a read request therefor is not present.

In the second read mode CASE2, the operation control circuitry 196 mayselect and read target data corresponding to a read request andadditional data together. For example, as illustrated in FIG. 10, ifdata stored in two sections Sec.0 and Sec.1 of the four sections Sec.0,Sec.1, Sec.2, and Sec.3 included in one page is target datacorresponding to a read request, the second read mode CASE2 may be anoperation of reading target data stored in the two sections Sec.0 andSec.1 and additional data stored in the remaining sections Sec.2 andSec.3 together. In this case, in the second read mode CASE2, the datastored in the two sections Sec.0 and Sec.1 of the four sections Sec.0,Sec.1, Sec.2, and Sec.3 included in the page may be cached in the pagebuffer and then read as the target data in response to the read request.In contrast, the data stored in the remaining two sections Sec.2 andSec.3 may be cached in the page buffer and then read as the additionaldata although a read request therefor is not present.

FIGS. 11A to 11C illustrate a first operation of the controller 130 formultiple read requests. Specifically, the first operation may beperformed by the pending credit determining circuitry 195 and thecorrelation circuitry 194 described with reference to FIG. 6.Furthermore, a plurality of read requests described in the firstoperation may be read requests received from the host or read requestsinternally generated by the controller. Furthermore, data correspondingto the plurality of read requests described in the first operation maybe data that is read-requested through an internal operation of thecontroller or random data that is read-requested by the host.

Specifically, referring to FIGS. 11A to 11C, it is assumed that aplurality of base read requests received from the host 102 (refer toFIGS. 2 and 3) or generated within the controller 130 has been input andstored in the input buffer 186. The plurality of base read requestsstored in the input buffer 184 may be arranged in input order from thehost. It is assumed that the plurality of base read requests includessix read requests R1 to R6.

The read requests R1 to R6 received from the host 102 or generatedwithin the controller 130 have a structure, such as the same code,according to an agreed protocol, but a sequence of 1 to 6 has beenincorporated and illustrated in FIGS. 11A to 11C, for convenience ofdescription.

A read request of the read requests R1 to R6 that is transmitted to thehost 102 may be transmitted along with a logical address (notillustrated). In such a case, the correlation circuitry 194 may identifyto which memory die a corresponding read request needs to be transmittedusing logical addresses, received along with the base read requests R1to R6, with reference to the map memory 182 (refer to FIG. 6).

Referring to <A> of FIG. 11A, it may be seen that the first and secondof the six base read requests R1 to R6 stored in the input buffer 186are selected as candidate read requests. Furthermore, it may be seenthat a pending credit has been reset to 0.

A correlation may not be performed on the first base read request R1because it is the only candidate read request present when R1 isselected as a candidate read request.

Next, while it is possible that the second base read request R2 becomesa target of a correlation operation because two candidate read requestsR1 and R2 are present when the second base read request R2 is selectedas a candidate read request, such correlation operation may not beperformed because the pending credit is 0, which is less than 2, thatis, a reference value.

Thereafter, the first candidate read request R1 is transmitted to anyone of the multiple memory dies and processed (S90) without having beensubjected to a correlation operation. At this time, the second candidateread request R2 may be in a pending state because the first candidateread request R1 is being processed.

The pending credit determining circuitry 195 may increase the pendingcredit by 3 in response to the processing of the first candidate readrequest R1 without a correlation operation (S90) as described above. Inthis case, the time at which the pending credit determining circuitry195 increases the pending credit may be the time at which the third baseread request R3 is selected as a candidate read request. That is, whenthe third base read request R3 is selected as a candidate read requestin <B> of FIG. 11A, the pending credit determining circuitry 195 mayincrease the pending credit as a result of the first candidate readrequest R1 having been processed without a correlation operation (S90)in <A> of FIG. 11A. While the presently described scenario entail anincrease in the pending credit when the process proceeds from <A> ofFIG. 11A to <B> of FIG. 11A, in a different scenario the pending creditmay decrease.

Referring to <B> of FIG. 11A, it may be seen that the third base readrequest R3 of the six base read requests R1 to R6 stored in the inputbuffer 186 is selected as a candidate read request. Furthermore, apending credit is 3.

At the time at which the third base read request R3 is selected as thecandidate read request, a correlation operation may be performed becausethe second candidate read request R2 is pending and the pending creditis more than the reference value. That is, a correlation operation maybe performed on the third candidate read request R3.

Accordingly, the correlation circuitry 194 may determine whether amemory die corresponding to the third candidate read request R3 and amemory die corresponding to the second candidate read request R2 arecorrelated. In this scenario, as a result of the correlation operation,the memory die corresponding to the third candidate read request R3 andthe memory die corresponding to the second candidate read request R2cannot be correlated, that is, the correlation operation fails (S91). Atthis time, the second and third candidate read requests R2 and R3 may bein a pending state because the first candidate read request R1 is beingprocessed (or has been processed).

The pending credit determining circuitry 195 may decrease the pendingcredit by 1 in response to the failure of the correlation operation onthe third candidate read request R3. In this case, the time at which thepending credit determining circuitry 195 decreases the pending creditmay be the time at which the fourth base read request R4 is selected asa candidate read request. That is, when the fourth base read request R4is selected as the candidate read request in <C> of FIG. 11B, thepending credit determining circuitry 195 may decrease the pending creditas a result of the correlation operation on the third candidate readrequest R3 having failed (S91) in <B> of FIG. 11A.

Referring to <C> of FIG. 11B, it may be seen that the fourth base readrequest R4 of the six base read requests R1 to R6 stored in the inputbuffer 186 is selected as a candidate read request. Furthermore, apending credit is 2.

At the time at which the fourth base read request R4 is selected as thecandidate read request, a correlation operation may be performed becausethe second and third candidate read requests R2 and R3 are pending andthe pending credit is the reference value or more. That is, acorrelation operation may be performed on the fourth candidate readrequest R4.

Accordingly, the correlation circuitry 194 may determine whether amemory die corresponding to the fourth candidate read request R4 may becorrelated with the memory die corresponding to the second candidateread request R2 or the memory die corresponding to the third candidateread request R3. Here, as a result of the correlation operation, thememory die corresponding to the fourth candidate read request R4 and thememory die corresponding to the second candidate read request R2 can becorrelated, that is, the correlation operation is successful (S92).

The pending credit determining circuitry 195 may increase the pendingcredit by 4 in response to the success of the correlation operation onthe fourth candidate read request R4. In this case, the time at whichthe pending credit determining circuitry 195 increases the pendingcredit may be the time at which the fifth base read request R5 isselected as the candidate read request. That is, when the fifth baseread request R5 is selected as the candidate read request in <D> of FIG.11B, the pending credit determining circuitry 195 may increase thepending credit as a result of the correlation operation on the fourthcandidate read request R4 having been successful (S92) in <C> of FIG.11B.

Referring to <D> of FIG. 11B, it may be seen that the fifth base readrequest R5 of the six base read requests R1 to R6 stored in the inputbuffer 186 is selected as a candidate read request. Furthermore, apending credit is 6.

At the time at which the fifth base read request R5 is selected as thecandidate read request, a correlation operation may be performed becausethe third candidate read request R3 is pending and the pending credit ismore than the reference value. That is, the correlation operation may beperformed on the fifth candidate read request R5. At this time, thesecond candidate read request R2 and the fourth candidate read requestR4 cannot be selected as read information for the correlation operationof the fifth base read request R5 because they have already beencorrelated.

Accordingly, the correlation circuitry 194 may determine whether amemory die corresponding to the fifth candidate read request R5 and thememory die corresponding to the third candidate read request R3 may becorrelated. In this scenario, as a result of the correlation operation,the memory die corresponding to the fifth candidate read request R5 andthe memory die corresponding to the third candidate read request R3cannot be correlated, that is, the correlation operation fails (S93). Atthis time, the third and fifth candidate read requests R3 and R5 may bein a pending state because the first candidate read request R1 is beingprocessed (or has been processed).

The pending credit determining circuitry 195 may decrease the pendingcredit by 2 in response to the failure of the correlation operation onthe fifth candidate read request R5. In this case, the time at which thepending credit determining circuitry 195 decreases the pending creditmay be the time at which the sixth base read request R6 is selected as acandidate read request. That is, when the sixth base read request R6 isselected as the candidate read request in <E> of FIG. 11C, the pendingcredit determining circuitry 195 may decrease the pending credit as aresult of the correlation operation on the fifth candidate read requestR5 having failed (S93) in <D> of FIG. 11B.

For reference, it may be seen that the pending credit is decreased by 1in response to the failure of the correlation operation on the thirdcandidate read request R3 in <B> of FIG. 11A, and the pending credit isdecreased by 2 in response to the failure of the correlation operationon the fifth candidate read request R5 in <D> of FIG. 11B. That is, itmay be seen that in both cases, the pending credit determining circuitry195 decreases the pending credits in response to the respective failuresof the correlation operations but by different amounts. The reason forthis is that the time consumed due to the failure of the correlationoperation on the third candidate read request R3 is shorter than thetime consumed due to the failure of the correlation operation on thefifth candidate read request R5. Thus, the pending credit is decreasedmore as a result of the failure of the correlation operation on R5 thanas a result of the failure of the correlation operation on R3.

Referring to <E> of FIG. 11C, it may be seen that the sixth base readrequest R6 of the six base read requests R1 to R6 stored in the inputbuffer 186 is selected as a candidate read request. Furthermore, it maybe seen that a pending credit is 4.

At the time at which the sixth base read request R6 is selected as thecandidate read request, a correlation operation may be performed becausethe third and fifth candidate read requests R3 and R5 are pending andthe pending credit is more than the reference value. That is, thecorrelation operation may be performed on the sixth candidate readrequest R6.

Accordingly, the correlation circuitry 194 may determine whether amemory die corresponding to the sixth candidate read request R6 may becorrelated with the memory die corresponding to the third candidate readrequest R3 or the memory die corresponding to the fifth candidate readrequest R5. Here, as a result of the correlation operation, the memorydie corresponding to the sixth candidate read request R6 cannot becorrelated with the memory die corresponding to the third candidate readrequest R3 or the memory die corresponding to the fifth candidate readrequest R5, that is, the correlation operation fails (S94).

The pending credit determining circuitry 195 may decrease the pendingcredit in response to the failure of the correlation operation on thesixth candidate read request R6 as described above.

In this case, the pending credit determining circuitry 195 may decreasethe pending credit when another base read request is additionallyselected as a candidate read request within a reference time after thesixth base read request R6 is selected as the candidate read request.

However, referring to <F> of FIG. 11C, after the sixth base read requestR6 is selected as the candidate read request, another base read requestis not selected as a candidate read request for the reference time ormore (S95). That is, after all of the six base read requests R1 to R6stored in the input buffer 186 are selected as the candidate readrequests and processed, another base read request is not received forthe reference time or more or is received during that time but notselected as a candidate read request due to an operating state of thememory system 110.

Accordingly, the pending credit determining circuitry 195 may notdecrease the pending credit in response to the failure of thecorrelation operation on the sixth candidate read request R6.

Furthermore, after the sixth base read request R6 is selected as thecandidate read request, the pending credit may be reset to 0, that is,an initial value, in response to the non-selection of a candidate readrequest for the reference time or more (S95).

Although various embodiments have been illustrated and described, itwill be apparent to those skilled in the art that various changes andmodifications may be made without departing from the spirit and scope ofthe invention as defined in the following claims. The present inventionencompasses all changes and modifications that fall within the scope ofthe claims.

What is claimed is:
 1. A memory system comprising: a memory deviceincluding plural dies, each having plural pages, each having pluralsections; and a controller electrically coupled to the dies throughplural channels respectively and suitable for providing the dies withread commands requesting data to be read from sections of differentoffsets within the respective dies, and controlling the dies to read therequested data according to a full sync interleaving scheme, wherein thecontroller controls each of the dies to perform a read operation inunits of the sections or in units of the pages according to a type of acorresponding read command among the provided read commands.